Senior SOC/ASIC Physical Design Engineer, Silicon Engineering
SpaceXJob Title
Senior SOC/ASIC Physical Design Engineer, Silicon Engineering
Role Summary
Implement and sign off physical design flows for next-generation SOC/ASIC chips used in Starlink space and ground systems. Work closely with systems, firmware, architecture, design, validation, and product teams to meet timing, power, area and reliability targets for production silicon.
Drive methodology and automation improvements to enable repeatable, production-quality tapeouts for mission-critical applications.
Experience Level
Senior; requires 5+ years of ASIC and/or physical design flow development experience.
Responsibilities
Primary tasks include physical implementation, signoff, and methodology development for complex SOC/ASIC designs.
- Perform synthesis, floorplanning, power/ground grid generation, place-and-route, timing closure, noise analysis, and physical verification.
- Develop and improve physical design methodologies and automation scripts for implementation and signoff steps.
- Collaborate with ASIC/design teams to set timing, power, and area targets and evaluate RTL/design tradeoffs.
- Identify, debug, and resolve timing, congestion, power integrity, electromigration, and other implementation issues.
- Run, debug, and fix signoff closure issues in static timing analysis, logic equivalency, DRC/LVS, electromigration, and IR drop.
Requirements
Must-have qualifications and constraints for this role; preferred items listed below.
- Must-have: 5+ years of industry ASIC and/or physical design flow development experience.
- Must-have: Practical experience with synthesis, place-and-route, timing closure, STA, and signoff flows.
- Must-have: Strong scripting skills (bash/csh, Python, Perl, TCL, Makefile) to develop automation.
- Must-have: Familiarity with industry-standard EDA tools and their capabilities.
- Must-have: Ability to work extended hours and weekends as needed to meet critical project milestones.
- Must-have: ITAR eligibility: U.S. citizen or national, lawful permanent resident (green card), refugee, asylee, or eligible to obtain required U.S. Department of State authorizations. (ITAR information)
- Nice-to-have: Experience with RTL-to-GDSII physical design and signoff flows.
- Nice-to-have: Knowledge of FinFET/CMOS device physics, standard cell libraries, DFT (Scan/MBIST/LBIST), and analog physical design considerations.
Education Requirements
Required: Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
About the Company
Company: SpaceX
Headquarters: Hawthorne, California, United States
SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.
