Senior SOC/ASIC Physical Design Engineer (Silicon Engineering)
SpaceXJob Title
Senior SOC/ASIC Physical Design Engineer (Silicon Engineering)
Role Summary
Work on end-to-end physical implementation and signoff for next-generation SOC/ASICs used in space and ground systems for the Starlink program. Collaborate with systems, firmware, architecture, validation, and implementation teams to deliver production silicon.
Responsible for developing and automating physical design methodologies, resolving timing/power/congestion issues, and driving designs from RTL through GDSII signoff.
Experience Level
Senior — 5+ years of ASIC and/or physical design flow development experience in industry.
Responsibilities
Key day-to-day responsibilities include:
- Perform partition synthesis and full physical implementation steps (synthesis, floorplanning, power/ground grid, place-and-route, timing, noise, physical verification, electromigration, IR drop, logic equivalency and other signoff checks).
- Develop and improve physical design methodologies and automation scripts for implementation and signoff flows.
- Collaborate with ASIC design and architecture teams to define timing, power, and area targets and evaluate RTL/design tradeoffs.
- Identify and resolve design, timing and congestion issues; propose and drive technical solutions to closure.
- Run, debug, and fix signoff closure issues across STA, noise, physical verification, EM/IR and equivalency checks.
- Drive execution to meet project milestones and signoff requirements.
Requirements
Must-have technical skills, compliance and work expectations:
- Proven experience with ASIC/SoC physical design and signoff flows (RTL-to-GDSII).
- Practical knowledge of static timing analysis, placement-and-route, power/ground design, noise analysis, DRC/LVS, EM and IR analysis.
- Experience with industry-standard EDA tools and understanding of their algorithms and limitations.
- Proficient scripting skills for automation (Python, TCL, Perl, shell, Makefiles, etc.).
- ITAR eligibility: U.S. citizen, U.S. lawful permanent resident, refugee, asylee, or otherwise eligible to obtain required U.S. Department of State authorizations.
- Ability to work extended hours and weekends as needed to meet critical project milestones.
Nice-to-have:
- Deep sub-micron FinFET/CMOS process knowledge and CMOS digital design principles.
- Familiarity with analog physical design, DFT (scan/MBIST/LBIST) and their impact on physical flows.
- Strong background in power optimization, leakage/dynamic power tradeoffs, and signoff closure techniques.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science required (as stated in the posting).
About the Company
Company: SpaceX
Headquarters: Hawthorne, California, United States
SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.
