Senior SoC Architect — Unified Intel Chassis (UIC) IP & Platform Architecture

Job Title

Senior SoC Architect — Unified Intel Chassis (UIC) IP & Platform Architecture

Role Summary

Lead definition and delivery of architecture specifications for Unified Intel Chassis (UIC) IP components and platform-level integration. The role combines architecture definition, implementation-awareness, and ownership of performance and power optimization across product generations.

Experience Level

Senior. Typical background: ~6+ years relevant experience (or ~4+ years with an MS degree) in SoC IP or subsystem architecture and platform performance.

Responsibilities

Define and validate IP and platform architecture, drive performance closure, and partner with cross-functional teams to ensure implementations meet targets.

• Author and maintain architecture specifications for UIC IP components and subsystem integration.
• Ensure architectures are implementation-aware, scalable, and power-optimized for multiple product generations.
• Drive platform performance analysis, identify bottlenecks, and lead optimization and closure activities.
• Build and enhance performance environments, models, and benchmarking flows.
• Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
• Specify architecture trade-offs, assumptions, interfaces, and measurable success criteria.
• Support debuggability, safety, reliability, and serviceability requirements in architecture definitions.
• Collaborate with system architects, RTL/design, verification, firmware/software, and performance teams.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven experience in SoC IP architecture for high-bandwidth interconnects or subsystem design.
• Practical experience with AMBA protocols (AXI, CHI, APB) — at least 1 year working with these protocols.
• Experience producing high-quality architecture specifications consumed by design and verification teams.
• Hands-on experience with power-optimization techniques and PPA (power/performance/area) trade-offs.
• Experience defining interface contracts, performance targets, and measurable success criteria.
• Strong collaboration and communication skills across architecture and implementation teams.
• Familiarity with AI tools to produce machine-readable specification documents (spec2silicon workflows).

Nice-to-have:

• Deep understanding of coherency concepts and CHI architecture.
• Expertise in arbitration and routing algorithms, end-to-end QoS, and low-latency scalable designs.
• Experience with fabric-based scalable platforms and cross-generation portability.
• Exposure to performance modelling, simulation, and data-driven architecture tuning.
• In-depth knowledge of cache architecture, MMU/IOMMU, security/access control, DVFS, distributed power management, and RAS/debug architectures.

Education Requirements

B.Tech / M.Tech / BS or MS in Computer Science, Electrical Engineering, or a related technical discipline. Minimum experience expectations noted in source: B.Tech/BS/M.Tech with ~6+ years relevant experience, or MS with ~4+ years relevant experience. (No other certifications specified.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.