Senior SoC Architect

Job Title

Senior SoC Architect

Role Summary

Lead definition and delivery of SoC IP and subsystem architecture for the Unified Intel Chassis (UIC). The role combines architecture specification, implementation awareness, and ownership of platform-level performance and power. Work closely with system architects, RTL/design, verification, firmware/software, and performance teams to enable scalable, implementation-ready architectures.

Experience Level

Senior. Typical experience: Bachelor's degree + 6+ years relevant experience, or Master's degree + 4+ years. Includes demonstrated SoC IP architecture and cross-functional collaboration experience.

Responsibilities

Define, document, and drive architecture and performance closure for UIC IP components and integrations.

• Author architecture specifications for UIC IP components and subsystem integration.
• Ensure architectures are implementation-aware, scalable, and power-optimized.
• Drive platform performance analysis, identify bottlenecks, and lead optimization and closure.
• Build and maintain platform performance environments, models, and benchmarking flows.
• Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
• Partner with architecture, design, verification, firmware/software, and performance teams to align on interfaces, trade-offs, and success criteria.
• Support debuggability, safety, reliability, and serviceability requirements in architecture definitions.
• Scope covers coherent and non-coherent fabrics, protocol adaptors (AXI, CHI, CXL, UAL), cache controllers, MMU/IOMMU, power management, debug/analytics, and security IP.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: Experience in SoC IP architecture or subsystem design for high-bandwidth interconnects.
• Proven ability to write high-quality architecture specifications consumed by design and verification teams.
• Hands-on experience with power-optimization techniques and making power/performance/area trade-offs.
• Experience defining interface contracts, performance targets, and measurable success criteria.
• Familiarity and 1+ year experience working with AMBA protocols (AXI, CHI, APB).
• Demonstrated cross-functional collaboration with implementation and performance teams.
• Nice-to-have: Expertise in coherency concepts and CHI, arbitration and routing algorithms, end-to-end QoS, fabric-based scalable platforms, performance modeling/simulation, cache/MMU/IOMMU internals, security/access-control frameworks, DVFS/distributed power management, and RAS/debug/safety architectures.
• Experience using AI or automation tools to produce machine-readable specifications for faster Spec-to-Silicon flows is a plus.

Education Requirements

Required: Bachelor's degree in Computer Science, Electrical Engineering, or a related discipline with 6+ years of relevant experience; OR Master's degree in Computer Science, Electrical Engineering, or a related discipline with 4+ years of relevant experience. (No substitute or equivalency language was specified.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.