Senior Silicon Engineer

Job Title

Senior Silicon Engineer

Role Summary

Senior DFT (Design for Test) engineer on the Microsoft Compute Silicon & Manufacturing Engineering team, responsible for block-level DFT architecture, timing closure and signoff, and supporting post-silicon debug for cloud server SoCs.

Work cross-functionally with Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams to improve manufacturability, quality, and delivery at scale.

Experience Level

Senior — requires over 5 years of professional experience in DFT and STA-related roles.

Responsibilities

Primary deliverables and day-to-day responsibilities include:

• Define and own block-level DFT architecture, specifications, and implementation for logic and memory test solutions (Scan, MBIST, LBIST, IJTAG, in-system test).
• Drive DFT timing closure and signoff, develop and maintain DFT STA constraints, timing exceptions, and signoff methodologies across the design cycle.
• Ensure robust timing of DFT infrastructure: test clocks, OCCs, clock muxing, and clock-gating architecture.
• Analyze and resolve DFT timing issues in complex multi-clock and low-power designs using advanced STA techniques.
• Develop automation and AI-assisted workflows to improve timing analysis, signoff efficiency, and productivity.
• Support post-silicon debug by correlating timing analysis with silicon test results and driving root-cause resolution.
• Provide technical leadership and collaborate with cross-functional teams to deliver high-quality silicon.

Requirements

Must-have technical skills, screening requirements, and preferred capabilities.

• Must-have: 5+ years of hands-on experience in DFT and STA (timing closure/signoff for test modes).
• Must-have: Practical knowledge of industry-standard DFT practices: ATPG, JTAG, Memory BIST, trade-offs between test quality and test time.
• Must-have: Experience developing DFT STA constraints and performing Primetime STA analysis for DFT/test modes, including CDC/RDC analysis.
• Must-have: Experience analyzing timing in complex multi-clock and low-power designs; familiarity with test clocks, clock gating and clock muxing for DFT.
• Must-have: Strong scripting and automation skills (Tcl, Perl or similar) to generate SDCs and automate flows; experience introducing automation or AI-assisted workflows is expected.
• Must-have: Ability to collaborate across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams.
• Must-have (screening): Ability to pass Microsoft Cloud Background Check and satisfy export-control eligibility (citizenship/residency verification as required).
• Nice-to-have: Experience with scan architecture and micro-architecture for large SoCs, including scan insertion for PLLs, I/Os and power circuits.
• Nice-to-have: Hands-on experience with EDA DFT tools (e.g., Siemens Tessent, Synopsys TestMax) and SoC toolflows; experience with implementation tools at advanced nodes (Genus, Fusion Compiler).
• Nice-to-have: Proven track record of proactive problem solving, delivering under pressure, and mentoring or technical leadership experience.

Education Requirements

BS, MS, or PhD in Electrical Engineering or Computer Engineering (degrees explicitly listed in the posting).

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.