Principal DFT Engineer, Silicon Engineering

Job Title

Principal DFT Engineer, Silicon Engineering

Role Summary

Lead the design-for-test (DFT) strategy and implementation for next-generation ASICs used in space and ground Starlink infrastructure. Work cross-functionally with architecture, RTL design, validation, physical design, and test teams to ensure testability and post-silicon validation through tapeout and product deployment.

Experience Level

Senior level — requires extensive ASIC and DFT experience; posting specifies 10+ years of ASIC and DFT experience.

Responsibilities

Primary responsibilities focus on DFT architecture, ATPG, integration, and post-silicon support:

• Lead implementation and optimization of DFT architectures (scan insertion, compression/decompression, memory BIST, logic BIST) using Siemens Tessent for RTL and gate netlist flows.
• Own ATPG flow and methodologies: generate patterns for stuck-at, transition, and path-delay faults; focus on pattern compression, diagnosis, and hierarchical test flows.
• Evaluate design readiness for scan insertion and run RTL and physical design Scan DRC checks.
• Integrate and verify DFT fabrics and IP within subsystems; provide post-silicon testing and validation support.
• Run and debug non-timing and SDF-annotated gate-level simulations.
• Develop test automation and analysis scripts using Perl, Python, Tcl, or C/C++.
• Collaborate with test engineering and ATE teams to validate production testing.

Requirements

Must-have technical skills and constraints; preferred items listed where applicable.

• Must-have: 10+ years of ASIC experience; 10+ years in scan insertion, DFT setup, integration and validation.
• Must-have: Hands-on experience with ATPG and pattern generation, diagnosis, and compression techniques.
• Must-have: Experience with Siemens Tessent or equivalent DFT tool flows and gate-level DFT implementation.
• Must-have: Ability to run and debug gate-level simulations and SDF-annotated flows.
• Must-have: Proficiency in scripting and automation (Perl, Python, Tcl, or C/C++).
• Must-have: Authorization constraint: must meet ITAR eligibility (U.S. citizen, U.S. national, lawful permanent resident, refugee, or asylee) or be able to obtain required authorizations.
• Nice-to-have: Leadership experience driving SoC DFT from concept through tapeout and product deployment.
• Nice-to-have: RTL experience for tracing and debugging connectivity issues; strong Verilog/SystemVerilog skills.
• Nice-to-have: Experience with UPF, formal verification, DRC rule checking, advanced process nodes, and ATE/test flow integration.
• Other: Willingness to work extended hours and weekends as needed to meet critical milestones.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science is specified.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.