Senior Silicon Design Engineer — DFx Verification

Job Title

Senior Silicon Design Engineer — DFx Verification

Role Summary

Senior member of the Radeon Technologies Group front-end design and integration team responsible for DFx verification at block, subsystem, and SoC levels to enable first-pass silicon success.

Work closely with architecture, IP design, physical design, and product engineering to define verification plans, close coverage gaps, and support silicon bring-up.

Experience Level

Senior-level. Title indicates senior role; years of experience not specified (typically 7+ years for similar roles).

Responsibilities

Primary responsibilities include planning, implementing, and executing DFx verification across design stages and collaborating with cross-functional teams.

• Own DFx verification at block/IP, subsystem, and SoC level (scan/ATPG, LBIST/MBIST, JTAG/1149.x, boundary scan, test compression, repair, debug).
• Develop and maintain SystemVerilog/UVM testbenches and tests, including stimulus, checkers, coverage, and scoreboards.
• Define and execute DFx verification plans from specs/requirements; track and close using coverage-driven metrics.
• Build and maintain BFMs, agents, and monitors to verify interactions between DFx logic and key functional blocks (clocks, resets, power, fabric, memories).
• Develop directed and constrained-random tests for scan insertion, BIST, repair flows, test access, and debug/trace logic.
• Run gate-level simulations (including scan-inserted netlists with SDF) to validate DFx behavior, test modes, and power-up/reset sequences.
• Partner with DFT/DFx architects and RTL designers to review micro-architecture, catch corner cases, and drive DFx-friendly designs.
• Work with post-silicon and product engineering to correlate pre-silicon DFx results with silicon, support bring-up, pattern debug, and yield/quality improvement.
• Analyze coverage, identify gaps, and enhance test content and infrastructure to achieve DFx verification closure.
• Maintain and improve DFx regression, debug, and automation flows (scripting, dashboards, CI).

Requirements

Key technical skills and experience required or strongly preferred for this role.

• Must-have: Strong experience in digital design verification using SystemVerilog and UVM (or similar methodologies).
• Must-have: Hands-on knowledge of DFT/DFx concepts and flows: scan, test compression, ATPG, LBIST, MBIST, JTAG/IEEE 1149.x, boundary scan, and test access mechanisms.
• Must-have: Understanding of SoC/CPU/GPU or complex ASIC design, including clocks, resets, CDC, and power intent (UPF/low-power modes) as they relate to DFx.
• Must-have: Proficiency in C/C++ and/or SystemVerilog DPI for modeling or test content generation.
• Must-have: Strong scripting skills (Python, Perl, Tcl, or Shell) for automation, regressions, and data analysis.
• Must-have: Experience with gate-level simulations and familiarity with EDA tools and flows (simulation, coverage, lint, formal, ATPG/DFT).
• Must-have: Effective communication and experience collaborating across sites/timezones; strong analytical and problem-solving skills.
• Nice-to-have: Experience with hardware emulation or FPGA prototyping for DFx validation.
• Nice-to-have: Experience in silicon bring-up, lab debug, or production test.
• Nice-to-have: Background in computing/graphics or high-performance SoCs.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.