Job Title
Senior Signal Integrity Engineer – LPU Packaging
Role Summary
Join the Packaging and Systems team to lead signal integrity design and simulation for high-speed SerDes channels across die, package, board, connector, and cable interfaces for data center and HPC platforms.
Work across silicon, package, board, and system boundaries to develop robust high-speed interconnect solutions, perform simulation-to-measurement correlation, and support interface bring-up and validation.
Experience Level
Senior — typically 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles.
Responsibilities
Key responsibilities include design, simulation, correlation, and cross-functional integration:
- Lead SI design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable.
- Develop and execute simulation flows for advanced packaging (2.5D, 3D, multi-die) focusing on channel loss, discontinuities, return path behavior, and crosstalk.
- Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems.
- Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures.
- Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met.
- Correlate simulation with lab measurements (TDR, VNA, oscilloscope) to improve model accuracy and signoff confidence.
- Support interface bring-up, debug, and margin analysis; translate correlation learnings into improved design methods and reusable flows.
- Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs.
Requirements
Must-have skills and experience:
- 8+ years industry experience in signal integrity, high-speed interconnect design, or related hardware development.
- Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior.
- Proven experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale systems.
- Hands-on experience with SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent.
- Experience building and using channel models, S-parameters, IBIS-AMI flows, and time/frequency-domain analysis techniques.
- Deep understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets.
- Experience with simulation-to-measurement correlation and lab-based model validation using VNA, TDR, and high-speed scope measurements.
- Ability to work effectively across cross-functional teams and drive technical decisions in a fast-moving product environment.
Nice-to-have:
- Experience with package and system SI for PCIe, CXL, NVLink, Ethernet, or other high-speed compute and networking interfaces.
- Deep knowledge of advanced packaging structures, substrate technologies, and chip-package-board co-design.
- Background in SI design for data center, AI infrastructure, or HPC platforms.
- Experience improving SI signoff methodology, building reusable automation flows, or driving design rule development.
- Familiarity with mixed-domain tradeoffs across SI, PI, thermal, mechanical, and manufacturability considerations.
Education Requirements
BS, MS, or PhD in Electrical Engineering, or equivalent practical experience.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

Date Posted: 2026-08-19