Senior Signal Integrity Engineer (Hands-on)

Job Title

Senior Signal Integrity Engineer (Hands-on)

Role Summary

Lead signal-integrity (SI) engineering for high-speed Ethernet and related interfaces within Intel's Central Engineering Group. Work across pre- and post-layout package and platform design, simulation, lab validation, and cross-functional debugging to ensure sign-off-quality channel performance.

Collaborate with silicon design teams, IP vendors, PCB/layout teams and test engineers; identify automation and AI-based methods to accelerate SI analysis and verification.

Experience Level

Senior - requires substantial hands-on SI experience; the posting specifies 7+ years of relevant Signal Integrity experience.

Responsibilities

Primary responsibilities include simulation, modeling, lab correlation, and technical leadership for SI across multiple projects.

• Model channel elements using 2D/3D EM and circuit simulators for pre- and post-layout stages of package and platform designs.
• Run sign-off simulation flows for PCIe, Ethernet and memory interfaces and provide actionable feedback to design teams.
• Correlate models with electrical and cross-section measurements; model manufacturing variation impacts.
• Perform hands-on lab measurements and debugging using oscilloscopes, VNA, TDR, BERT and related equipment.
• Lead SI activities and drive technical reviews, debugging sessions, and task-force deliverables.
• Work closely with silicon designers and Hard IP vendors to validate interfaces and compliance to specifications.
• Evaluate and qualify AI-based automation techniques and tools to improve SI workflows.

Requirements

Must-have skills and experience:

• Proven design experience in the semiconductor ASIC development industry.
• Practical knowledge of PCB technology and layout techniques including stack-up, routing, and SI/PI considerations.
• Hands-on experience with EM/field and SI EDA tools such as HFSS, CST, ADS, Simbeor or equivalents.
• Familiarity with PCB CAD tools (Cadence Allegro, Mentor Expedition or equivalent).
• Experience modeling and simulating at least one of: Ethernet, PCIe, or DDR interfaces.
• Lab measurement experience with high-speed, low-speed and clock signals (oscilloscopes, VNA, TDR, BERTs).
• Strong debugging skills, root-cause analysis, and the ability to deliver corrective actions.
• Ability to lead cross-functional teams and communicate effectively in English with engineering and program stakeholders.
• Working experience with AI-based tools applied to engineering workflows.

Nice-to-have:

• Exposure to PAM4 Ethernet 224Gb, PCIe Gen6/Gen7, DDR5/DDR6 interfaces and related specification work.
• Experience with automated SI sign-off flows and scriptable analysis environments.

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering (or a closely related technical field) is specified. The posting requests over 7 years of relevant Signal Integrity experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.