Senior Sensors Design Verification Engineer

Job Title

Senior Sensors Design Verification Engineer

Role Summary

Work within the Sensors Technologies group on functional verification of sensor algorithms and associated RTL for ASIC tapeout readiness. The role focuses on building UVM testbenches, integrating C models, running regressions, and collaborating with design and systems teams to close coverage and debug issues.

This is an engineering role contributing to verification flow development, automation, and project reviews for sensor subsystems in a high-volume ASIC development environment.

Experience Level

Senior — typically 4+ years of ASIC design verification or equivalent industry experience; minimum experience requirements vary by degree (see Education Requirements).

Responsibilities

Primary day-to-day responsibilities include developing verification infrastructure, exercising RTL with realistic test vectors, and driving closure of functional and code coverage targets.

• Design and implement UVM testbenches and verification components (UVCs, environment, test sequences).
• Integrate C models into the UVM framework and validate bit-exact behavior versus vectors.
• Write and maintain SystemVerilog assertions and support formal verification where applicable.
• Develop and execute test plans derived from design and system documents.
• Run and maintain regression frameworks; analyze failures and work with design/systems teams to debug.
• Analyze coverage data, identify holes, and drive remediation with design teams.
• Use RTL simulation tools extensively for verification and debug tasks.
• Automate workflows using Python/Perl and support cross-team debugging and documentation.

Requirements

Required skills and experience to perform the role.

• 4+ years of ASIC design verification, UVM-based functional verification, or equivalent experience.
• Proven experience with UVM and coverage-driven verification methodology.
• Strong SystemVerilog skills, including SystemVerilog Assertions (SVA).
• Extensive use of RTL simulation tools and experience debugging test failures.
• Scripting and automation skills: Python and/or Perl; shell scripting.
• Familiarity with C/C++ for model integration and test infrastructure.
• Strong analytical, written, and verbal communication skills; collaborative team player.

Nice-to-have:

• Experience with formal tools (e.g., Jasper, VC_Formal).
• Experience with SystemC, MATLAB, gate-level simulation, or power extraction tools.

Education Requirements

Bachelor's, Master's, or PhD in Science, Engineering, or a related field are referenced. The posting allows alternative paths: e.g., Bachelor's + 2+ years verification experience, Master's + 1+ year, or PhD (no minimum experience listed). Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.