Senior SDC Timing Constraints Engineer

Role Overview

We are seeking a highly skilled Member of Technical Staff (MTS) to join our Speedfiles team at Advanced Micro Devices in Hyderabad. This role involves driving timing capture across complex high-performance SoC and IP blocks, requiring collaboration with various teams including physical design, RTL, methodology, and architecture.

Expertise Level

This position is suited for candidates with 7–10 years of hands-on experience in static timing analysis (STA) for high-performance SoCs or IPs. Strong technical skills and a deep understanding of semiconductor timing fundamentals are required.

Key Responsibilities

• Own and execute block-level static timing capture including constraint development.
• Validate timing constraints (SDC) for different operational modes.
• Perform timing capture to identify and resolve timing issues across various corners and modes.
• Collaborate with RTL, physical design, and synthesis teams to optimize timing.
• Enhance timing capture flows, automation, reports, and signoff processes with the methodology team.
• Debug and address complex issues related to noise, crosstalk, OCV, POCV, AOCV, and IR-drop impacts.
• Support silicon bring-up by correlating pre-silicon STA results with post-silicon behavior.
• Document and present timing capture status and strategies to cross-functional teams and management.

Qualifications

The ideal candidate will hold a Bachelor’s or Master’s degree in Electronics Engineering, VLSI, or a related field. A solid grasp of timing fundamentals, industry-standard STA tools like Synopsys PrimeTime and Cadence Tempus, and proficiency in scripting languages such as TCL, Perl, Python, or Shell scripting is essential.

Education Requirements

Bachelor’s or Master’s degree in Electronics Engineering, VLSI, or a related field.