Senior RTL Design Engineer – Interconnect & Network Datapath

Job Title

Senior RTL Design Engineer – Interconnect & Network Datapath

Role Summary

Join OpenAI Hardware to design and implement packet-based interconnects and networking datapaths for a custom AI accelerator platform. The role leads microarchitecture and RTL implementation of on-chip fabrics, off-chip interfaces, and protocol bridges to meet performance, area, and power targets.

Experience Level

Senior-level. Years of experience not specified; this is a senior role with broad technical ownership and mentorship responsibilities.

Responsibilities

Accountable for end-to-end design, implementation, and delivery of packet-based interconnect and networking components.

• Own microarchitecture and RTL for NoCs, switches, routers, bridges, protocol adapters, queues, arbiters, schedulers, buffers, and traffic-management logic.
• Design routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring mechanisms.
• Develop on-chip and off-chip interfaces, protocol bridges, and custom protocol extensions for scale-up and scale-out systems.
• Perform substantial SystemVerilog coding, simulation, and debug; drive verification closure.
• Collaborate with architecture and performance teams to analyze traffic patterns and optimize latency, bandwidth, fairness, and utilization under realistic workloads.
• Work with verification and physical design teams on coverage plans, timing closure, floorplan-aware design, power, area, and physical congestion.
• Support firmware, software, validation, and post-silicon teams during bring-up and production readiness.
• Drive third-party IP engagements and provide technical leadership, documentation, and mentoring for junior engineers.

Requirements

Must-have technical qualifications and skills for successful performance in this role.

• Recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• Experience designing queues, arbiters, schedulers, buffers, virtual channels, credit-based flow control, congestion management, QoS, ordering, and deadlock-avoidance mechanisms.
• Proven track record owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.
• Familiarity with on-chip and chip-to-chip interfaces such as AXI, CHI, CXL, PCIe, or Ethernet and related protocol development.
• Strong familiarity with RTL signoff flows including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test.
• Ability to collaborate across architecture, verification, physical design, firmware, performance, and post-silicon teams and to mentor engineers while remaining hands-on.
• Nice-to-have: experience with NICs/SmartNICs/DPUs, RDMA/RoCE/InfiniBand, custom interconnects for AI/HPC, virtualization/isolation/RAS/telemetry, performance modeling, FPGA prototyping, or leading first-generation IP delivery.

Education Requirements

Not specified.

About the Company

Company: OpenAI

Headquarters: San Francisco, CA, USA

OpenAI is an AI research and deployment company that develops advanced AI models, tools, and products aimed at ensuring general-purpose artificial intelligence benefits all of humanity. The organization focuses on safety, scalability, and responsible deployment of AI technologies across research and production systems.