Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Senior RTL engineer in the ASIC/SoC engineering team working on connectivity networking SoCs. Responsible for microarchitecture, RTL coding, documentation, integration, and supporting verification, physical design, software and FPGA teams through tapeout.

Work focuses on high-performance, low-power SoC/subsystem IP for next-generation connectivity and AI datacenter products.

Experience Level

Senior-level. The role expects multi-year, multi-project RTL SoC design experience; the posting's minimum qualifications start at 1–2+ years depending on academic level but this position targets experienced engineers.

Responsibilities

Key responsibilities include design, verification support, and delivery of SoC/subsystem RTL.

• Define microarchitecture and implement RTL for SoC subsystems and IP blocks.
• Perform RTL quality checks (lint, CDC, LEC) and address issues reported by verification.
• Produce hardware design documentation and microarchitecture specifications.
• Develop synthesis constraints for blocks and subsystems.
• Collaborate with verification, physical design, software, and FPGA teams to meet area, power, performance, and tapeout goals.
• Work with SOC architects and leads to integrate designs, review/approve verification plans, and support DFT and PD implementation.

Requirements

Must-have skills and proven experience for immediate contribution; nice-to-have items are listed separately.

• Proven RTL SoC design experience across multiple projects using Verilog or VHDL.
• ASIC/FPGA debug methodologies and experience diagnosing RTL-to-silicon issues.
• Experience with synthesis flows (Design Compiler) and formal equivalence checking (LEC).
• Strong understanding of timing closure and timing-driven design practices.
• Ability to review test plans and coverage metrics and work with verification teams to close functional gaps.
• Good communication and teamwork skills; able to lead technical interactions across teams.
• Nice-to-have: experience with SerDes PHY, DSP, analog mixed-signal interfaces, Ethernet, PCIe, bus protocols (AHB/AXI), and peripheral IP integration.
• Nice-to-have: architecture and micro-architecture development experience based on specifications.

Education Requirements

Minimum qualifications in the posting: Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC-related experience; OR Master's degree in Science, Engineering, or related field with 1+ year of ASIC-related experience; OR PhD in Science, Engineering, or related field. The posting also states candidates with equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.