Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Design and implement RTL for a high-performance processing platform. The role works on digital microarchitecture, datapaths, control logic, memory subsystems, and on-chip interconnects, collaborating with architecture, verification, synthesis, and physical design teams to meet performance, power, and timing goals.

Experience Level

Senior level. Typical guidance: 4+ years of professional experience in RTL design and microarchitecture development.

Responsibilities

Key responsibilities include:

• Design and implement RTL components for next-generation processing platforms.
• Develop and optimize datapaths, control logic, memory subsystems, interconnects, and data-movement engines with a focus on performance and power.
• Contribute to microarchitecture definition and work with verification teams to validate functionality.
• Support timing closure in collaboration with synthesis and physical design groups.
• Participate in design reviews and improve RTL development practices and methodologies.

Requirements

Must-have technical skills and experience:

• 4+ years of RTL design and microarchitecture development experience.
• Strong understanding of computer architecture concepts such as pipelining, caching, and memory hierarchy.
• Experience in one or more of: interconnect design, data-movement engines, memory subsystems, or control/datapath logic.
• Proficiency in Verilog or SystemVerilog and standard RTL design practices.
• Familiarity with timing constraints, synthesis, physical design considerations, and timing analysis.
• Experience with simulation, synthesis, linting, and timing analysis tools.
• Strong analytical, problem-solving, and cross-team communication skills.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (degree required/preferred as specified).

About the Company

Company: Lumicity

Engineering firm focused on digital design and high-performance processing platforms; hires RTL design engineers to develop microarchitecture, datapaths, memory subsystems, and on-chip interconnects.