Senior RTL Design Engineer - CPU Frontend

Job Title

Senior RTL Design Engineer - CPU Frontend

Role Summary

Design and implement CPU frontend microarchitecture and RTL for RISC‑V cores. Develop features in generator-based flows, integrate work into the Chisel/FIRRTL framework, and coordinate with verification, physical implementation, and performance teams to meet functional, timing, area, and power targets.

This role focuses on CPU feature development, documentation, and cross-team engineering execution.

Experience Level

Senior — posting requires 3+ years of RTL design experience.

Responsibilities

Deliver microarchitectural features and integrate them into generator and verification frameworks; collaborate with implementation and performance teams.

• Architect, design, and implement features, ISA extensions, and performance improvements in RISC‑V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve tooling for automated configuration, documentation, verification benches, and packaged software.
• Perform initial sandbox verification and collaborate with the verification team to create and execute comprehensive test plans.
• Work with physical implementation to meet frequency, area, and power goals and optimize designs for silicon.
• Collaborate with performance modeling for exploration and optimization.
• Produce clear documentation and share design knowledge across teams.

Requirements

Must-have technical skills and experience.

• 3+ years of RTL design experience.
• Practical CPU RTL experience in one or more areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
• Proficiency in RTL languages such as Verilog, SystemVerilog, or VHDL.
• Strong software engineering background: functional and object-oriented programming, templated metaprogramming, compiler/DSL experience, data/IR modeling, and test-driven development.
• Attention to detail and ability to work collaboratively on engineering teams.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other hardware DSLs.
• Knowledge of RISC‑V architecture and advanced CPU topics (register renaming, instruction scheduling, vector units, load-store units).
• Familiarity with verification methodologies (UVM, coverage) and tools such as Git/GitHub, Jira, Confluence.

Education Requirements

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.