Senior RTL Design Engineer - CPU Frontend
SiFiveJob Title
Senior RTL Design Engineer - CPU Frontend
Role Summary
Design and implement CPU frontend RTL features and ISA extensions for RISC-V core generators. Integrate designs into the Chisel/FIRRTL toolchain and collaborate with verification, physical implementation, and performance modeling teams to meet performance, area, and power goals.
Experience Level
Senior — posting requests 3+ years of RTL/design experience; role expects experienced engineers able to own microarchitecture features and work cross-functionally.
Responsibilities
Primary responsibilities include architecture, RTL implementation, integration, verification, and optimization of CPU frontend components.
- Architect and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate design content into the Chisel/FIRRTL framework and improve tooling for automatic configuration, documentation, verification testbenches, and packaged software.
- Perform initial sandbox verification and coordinate with the design verification team to develop and execute verification plans.
- Collaborate with physical implementation engineers to meet frequency, area, and power targets.
- Work with performance modeling for exploration and optimization to meet performance goals.
- Develop microarchitecture specifications and maintain clear, shareable design documentation.
Requirements
Must-have technical skills and experience.
- 3+ years of RTL/design experience.
- Practical CPU RTL design experience in one or more of: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, or TLBs.
- Proficiency in Verilog, SystemVerilog, or VHDL.
- Strong software engineering skills: functional programming, templated metaprogramming, compiler infrastructures, data modeling for intermediate representations, and test-driven development.
- Attention to detail and ability to collaborate effectively in engineering teams.
Nice-to-have:
- Experience with Scala/Chisel, Bluespec, or other hardware-DSLs.
- Knowledge of RISC-V architecture.
- Expertise in advanced CPU areas such as register renaming, instruction scheduling, vector units, or load-store unit.
- Experience with verification principles, UVM, and coverage.
- Familiarity with Git/GitHub, Jira, and Confluence.
Education Requirements
BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
