Senior RTL Design Engineer - CPU Frontend

Job Title

Senior RTL Design Engineer - CPU Frontend

Role Summary

Design and implement CPU frontend features and performance improvements for RISC-V core generators. Integrate microarchitectural changes into the Chisel/FIRRTL toolchain and work with verification, physical implementation, and performance teams to deliver configurable, high-performance CPU cores.

Base pay range (US): $158,760 - $194,040.

Experience Level

Senior-level. The posting requests 3+ years of design experience.

Responsibilities

Primary responsibilities include architecture, RTL implementation, verification collaboration, and working with implementation and performance teams.

• Architect, design, and implement new features, ISA extensions, and performance improvements in RISC-V CPU cores using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve tooling for automatic configuration, verification testbenches, and documentation generation.
• Perform initial sandbox verification and coordinate with the verification team to create and execute verification plans.
• Work with physical implementation engineers to meet frequency, area, and power targets.
• Collaborate with performance modeling to explore and optimize CPU performance.
• Develop and document microarchitecture; share knowledge across teams.

Requirements

Must-have skills and experience required for the role.

• 3+ years of RTL design experience.
• Experience with CPU RTL in one or more areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware RTL: Verilog, SystemVerilog, or VHDL.
• Strong software engineering background: functional and object-oriented programming, templated metaprogramming, compiler infrastructures for DSLs, data modeling for IRs, and test-driven development.
• Attention to detail and commitment to high-quality design.
• Ability to work collaboratively in engineering teams.

Nice-to-haves

• Experience with Scala/Chisel, Bluespec, or similar hardware DSLs.
• Knowledge of RISC-V architecture.
• Expertise in advanced CPU topics: register renaming, instruction scheduling, vector units, load-store units.
• Familiarity with verification methodologies, testbenches, UVM, and coverage tools.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.