Senior RTL Design Engineer - CPU

Job Title

Senior RTL Design Engineer - CPU

Role Summary

Design and implement CPU microarchitecture and RTL for RISC‑V cores as part of a CPU core generator team in Cambridge. Work across architecture, RTL implementation, verification, and physical optimization to deliver production-quality processor IP.

Experience Level

Senior-level; requires 3+ years of design experience.

Responsibilities

Deliver microarchitecture and RTL features, integrate them into the generator framework, and collaborate on verification and physical implementation.

• Architect, design, and implement CPU features, performance improvements, and ISA extensions using Chisel.
• Integrate designs into the Chisel/FIRRTL framework and improve automation for configuration, verification, and documentation generation.
• Perform initial sandbox verification and coordinate with the verification team to create and execute test plans.
• Work with physical implementation teams to meet frequency, area, and power targets.
• Collaborate with performance modeling for exploration and optimization.
• Document microarchitecture and participate in collaborative design reviews.

Requirements

Key technical qualifications and skills. Must-haves listed first, followed by nice-to-have items.

• Must-have: Minimum 3 years of design experience; academic or professional experience with CPU RTL design.
• Must-have: Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Must-have: Strong software engineering background, including functional programming concepts, templated metaprogramming, compiler/DSL infrastructure, data modeling for intermediate representations, and test-driven development.
• Must-have: Attention to detail and ability to work effectively in engineering teams.
• Nice-to-have: Experience with Scala/Chisel or Bluespec; knowledge of RISC‑V; expertise in fetch/decode, renaming/scheduling, vector units, or load-store units; verification/testbench/UVM and coverage experience; familiarity with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.