Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Design RTL components for the Reconfigurable Dataflow Unit (RDU) ASICs used in SambaNova's AI acceleration systems. Work spans microarchitecture, RTL implementation, PPA trade-offs, quality gates, timing closure, and silicon bring-up.

Collaborate with architects, verification, physical design, and principal engineers to deliver production ASIC blocks and take ownership of increasingly larger subsystems.

Experience Level

Senior - role expects experienced engineers; the posting lists a minimum of 5+ years of ASIC RTL design experience.

Responsibilities

Primary responsibilities include end-to-end RTL design and delivery of ASIC blocks inside the RDU.

• Specify, design, and implement RTL blocks for compute datapath, on-chip network, and memory subsystems.
• Participate in microarchitecture design and PPA trade-off decisions (power, performance, area).
• Write, debug, and maintain SystemVerilog RTL for high-speed, high-performance designs.
• Drive quality gates: lint, CDC checks, logical equivalence checking (LEC), and SystemVerilog Assertions (SVA).
• Work through synthesis, static timing analysis, timing closure, and silicon bring-up activities.
• Collaborate with verification, physical design, emulation/FPGA teams, and system architects.

Requirements

Key technical requirements and preferred skills.

• 5+ years of practical ASIC RTL design experience.
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
• Solid foundation in computer architecture and digital logic design.
• Experience making design decisions that trade off power, performance, and area.
• Knowledge of interconnects and protocols such as AXI, PCIe, Ethernet, and HBM or DDR.
• Experience with digital logic synthesis tools and static timing analysis (STA).
• Proficiency with linting, CDC checking, and logical equivalence checking tools.
• Experience implementing SystemVerilog Assertions to validate design intent.
• Familiarity with hardware performance analysis and tuning tools and simulators.
• Experience using Git for release cycles and scripting in Python and Linux shell.
• Nice-to-have: exposure to full ASIC development cycle through tape-out, low-power techniques (clock gating, DVFS), emulation or FPGA prototyping, and knowledge of AI workload acceleration.

Education Requirements

Required: B.S. in Electrical Engineering, Computer Engineering, or Computer Science. Preferred: M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: SambaNova Systems

Headquarters: Palo Alto, CA, United States

Provider of a full‑stack generative AI platform that integrates custom AI accelerator hardware and software. SambaNova delivers the SambaNova Suite and SN40L chip to enable high-performance, on‑premises and cloud deployments for enterprise and government AI workloads.