Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Join the RTL design team responsible for the compute datapath, on-chip network, and memory subsystems of the RDU AI accelerator. Design, implement, and carry RTL blocks from microarchitecture through implementation, tape-out, and silicon bring-up while collaborating with architects, verification, and physical design teams.

Experience Level

Senior — typically 5+ years of ASIC RTL design experience, especially in high-performance, high-speed digital ASICs.

Responsibilities

Own RTL blocks within larger subsystems and drive them through design and delivery.

• Contribute microarchitecture specification and implement RTL for components of the RDU ASICs.
• Write, review, and debug SystemVerilog for high-speed, high-performance designs.
• Perform PPA trade-offs and optimize for power, performance, and area.
• Execute quality gates: lint, CDC, LEC, and participate in timing closure activities.
• Integrate and verify interfaces to interconnects/protocols (AXI, PCIe, Ethernet, HBM/DDR).
• Collaborate with design verification, physical design, and architects; support tape-out and silicon bring-up.
• Use scripting and automation (Python, shell) and Git to support release cycles and tooling.

Requirements

Must-have skills and experience:

• 5+ years of ASIC RTL design experience for high-performance chips.
• Strong SystemVerilog RTL design skills and experience implementing assertions.
• Experience with digital logic synthesis tools and static timing analysis.
• Familiarity with EDA flows/tools for linting, CDC, and logical equivalence checking.
• Experience with interconnects/protocols such as AXI, PCIe, Ethernet, and memory interfaces (HBM or DDR).
• Familiarity with hardware performance analysis tools and simulators.
• Proficiency with Git, Python, and Linux shell scripting.

Nice-to-have:

• Experience with low-power design techniques (clock gating, DVFS) at advanced nodes.
• Exposure to full ASIC development cycle including tape-out, FPGA prototyping, or emulation.
• Knowledge of AI workload acceleration techniques.

Education Requirements

Required: B.S. in Electrical Engineering, Computer Engineering, or Computer Science. Preferred: M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: SambaNova Systems

Headquarters: Palo Alto, CA, United States

Provider of a full‑stack generative AI platform that integrates custom AI accelerator hardware and software. SambaNova delivers the SambaNova Suite and SN40L chip to enable high-performance, on‑premises and cloud deployments for enterprise and government AI workloads.