Senior RTL Design Engineer

Job Title

Senior RTL Design Engineer

Role Summary

Hands-on RTL design engineer responsible for taking complex SoC units from architecture through tapeout. You will define microarchitecture, write synthesizable RTL, and work closely with synthesis, timing, power and test teams to meet functional and timing goals.

Experience Level

Senior - 7+ years of VLSI design experience.

Responsibilities

Contribute across the full RTL design flow and coordinate with cross-functional teams to deliver silicon-ready blocks.

• Lead feasibility studies and help define system architecture, requirements and external interfaces.
• Develop microarchitecture and logic design with functional leads from architecture to tapeout.
• Write RTL in Verilog and SystemVerilog; run lint and CDC checks (e.g., Synopsys VC SpyGlass).
• Create timing constraint files and support synthesis (e.g., Synopsys Design Compiler).
• Collaborate with synthesis, STA, PD and DFT teams to meet functional, performance, power and area targets.
• Debug and fix design issues; develop flows and scripts to support design and automation.

Requirements

Key technical skills and experience required for the role.

• Strong Verilog and SystemVerilog RTL design skills.
• Experience defining microarchitecture for complex design units and prior SoC design experience.
• Proficient in lint, CDC and low-power design practices.
• Working knowledge of synthesis and STA tools.
• Familiarity with ARM, RISC-V or x86 instruction set architectures.
• Scripting experience in Python and Tcl; Perl or C is a plus.
• Good understanding of verification methodologies.
• Excellent English and strong communication skills.

Education Requirements

BSc or MSc in Electrical or Computer Engineering.

About the Company

Company: Envision Employment Solutions

Headquarters: New Cairo City, Egypt

A recruitment and staffing firm that connects employers with candidates across industries, specializing in sourcing talent for technical and engineering roles.