Senior Reliability PDK and TFM Engineer
Intel CorporationJob Title
Senior Reliability PDK and TFM Engineer
Role Summary
Lead reliability design enablement for Intel foundry process nodes by developing and validating reliability-related PDK design rules, tool/flow/methodology (TFM), and collateral. Work with internal teams and EDA vendors to deliver verification flows, benchmarks, and IP ecosystem support to ensure design reliability and optimize PPA.
Experience Level
Senior-level. Typically requires multiple years of engineering experience in PDK, reliability, or EDA tool/flow development (see Education Requirements for formal experience equivalence).
Responsibilities
Primary responsibilities include defining reliability requirements, enabling tools and flows, and delivering verification and collateral to support customers and internal design teams.
- Define and generate reliability-related PDK design rules, collateral, QA processes, and benchmarking analysis covering reliability mechanisms.
- Drive EDA tool and flow enablement in coordination with PDK development and EDA vendors to deliver competitive TFM for reliability verification.
- Perform competitive analysis and benchmarking of technology reliability; plan and deliver PDK, design rules, TFM, and IP ecosystem improvements.
- Validate and verify reliability impacts across circuit, IP, and SoC design flows using PDK and EDA tools.
- Develop and maintain quality assurance methods and automation for techfile and design-rule generation.
- Coordinate with cross-functional teams and stakeholders to integrate reliability requirements into design flows and sign-off criteria.
- Document findings, present analyses, and support design teams with technical guidance for reliability risk mitigation.
Requirements
Must-have technical skills and experience; preferred items listed where applicable.
- Must-have: 3+ years' experience in at least one of: PDK development, reliability tool/flow development, design-for-reliability, or circuit/IP/SoC reliability validation using PDK and EDA tools.
- Must-have: Practical experience enabling or validating EDA tool flows and interacting with EDA vendors or internal tool teams.
- Must-have: Strong written/verbal communication, documentation, and presentation skills; ability to work in diverse, cross-functional teams.
- Must-have: Attention to detail, process discipline, and demonstrated ability to drive quality-improvement projects.
- Nice-to-have: Hands-on PDK validation, techfile generation automation, scripting or programming for rule/techfile generation and QA (Python, Tcl, or similar).
- Nice-to-have: Experience with reliability verification physics such as aging (BTI, HCI), electro-migration, high-voltage design issues, EOS/ESD.
- Nice-to-have: Program and stakeholder management experience coordinating multi-team deliverables.
Education Requirements
Minimum: Bachelor's degree in electrical engineering, physics, or a related field plus 6+ years relevant experience; OR Master's degree plus 4+ years relevant experience; OR PhD plus 2+ years relevant experience. Preferred: Master's or PhD in electrical engineering, physics, or related fields. Equivalent combinations of education and relevant work experience are considered per the above formulations.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
