Senior Principal VLSI/ASIC Design Engineer

Job Title

Senior Principal VLSI/ASIC Design Engineer

Role Summary

Lead architecture and detailed RTL design for complex VLSI components and system-on-chip (SoC) solutions, focused on networking, compute, and related high-performance applications. Serve as a technical authority, driving design decisions, implementation methodologies, and cross-functional integration toward production-ready ASICs.

Experience Level

Senior - typically requires 11+ years of experience in ASIC, VLSI, SoC, or related hardware design.

Responsibilities

Key responsibilities include early-stage exploration through delivery of production-ready designs and providing technical leadership across teams.

• Lead ASIC architecture and microarchitecture exploration for networking, compute, and SoC designs.
• Define architectural approaches, design methodologies, and implementation plans aligned with product and technology roadmaps.
• Design and develop complex RTL blocks using Verilog/SystemVerilog or comparable HDLs.
• Drive RTL implementation through synthesis, timing closure, and physical design interaction to production readiness.
• Analyze tradeoffs across performance, power, area, scalability, reliability, and schedule.
• Develop and validate models via simulation, prototyping, and empirical evaluation; establish performance expectations.
• Conduct and lead design reviews to ensure compliance with architecture and quality standards.
• Integrate new IP, tools, and methodologies into existing architectures and processes.
• Collaborate with architecture, verification, physical design, firmware, software, manufacturing, and external partners.
• Mentor engineers and provide technical direction as an internal subject-matter authority.

Requirements

Must-have technical skills and experience; preferred items marked accordingly.

• Must-have: Extensive experience (typically 11+ years) in ASIC/VLSI/SoC design and delivery.
• Must-have: Advanced knowledge of digital logic, RTL design, and SoC development.
• Must-have: Proven RTL development using Verilog, SystemVerilog, or equivalent.
• Must-have: Familiarity with full ASIC development flows: RTL coding, synthesis, timing analysis, physical-design interaction, and signoff.
• Must-have: Experience with design modeling, simulation, and performance analysis.
• Must-have: Strong analytical, problem-solving, and technical decision-making skills; ability to evaluate design alternatives and tradeoffs.
• Must-have: Strong written and verbal communication and the ability to influence across teams and senior leadership.
• Must-have: Experience mentoring engineers and providing technical leadership without direct management responsibility.
• Nice-to-have: Design verification experience (formal, constrained-random, coverage methodologies) and verification planning.
• Nice-to-have: Experience with networking ASICs, DPU, packet pipelines, memory subsystems, high-speed interfaces, low-power design, DFT, or working with outsourced partners, IP vendors, and foundries.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent practical experience may be considered.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.