Senior Principal Verification Engineer

Job Title

Senior Principal Verification Engineer

Role Summary

Join a verification engineering team responsible for developing and maintaining UVM-based verification environments and methodologies for system-level memory IP and related protocol blocks. The role focuses on delivering high-quality verification solutions for memory subsystems and supporting hardware-based verification products.

This position involves technical leadership on complex verification projects, cross-team collaboration, and mentoring junior engineers.

Experience Level

Senior-level. Typical guidance: 5–7+ years of relevant verification experience (Principal / T4 level).

Responsibilities

Main responsibilities include technical execution, environment development, and support:

• Design, develop, and maintain UVM-based verification environments for memory IP (SDRAM/LPDDRx/DDRx/HBMx), DFI PHY, UFS, and complex storage memory models.
• Plan and execute complex verification projects from requirements through delivery and post-delivery support.
• Analyze customer and vendor protocol requirements and verify product-wide features.
• Integrate tools and processes for coverage, reporting, and regression to build robust verification flows.
• Research and prototype tools, languages, and methodologies to improve verification effectiveness.
• Support product regression, OS compliance, automation, and release preparation.
• Mentor less experienced engineers and participate in cross-functional projects.

Requirements

Must-have technical skills and competencies:

• Expert knowledge of HDLs/HVLs, especially Verilog and SystemVerilog.
• Deep experience with UVM and SystemVerilog; strong C++ skills.
• Proven experience with simulation/emulation and EDA tools for debug and verification.
• Experience verifying multiple protocols (examples: UFS/Unipro/MPHY, SDRAM, Ethernet, PCIe, USB3/4, MIPI).
• Experience in functional verification of complex digital systems (SoC-level verification) using HVLs.
• Experience designing and implementing complex functional verification environments.
• Practical experience with process automation and scripting for verification flows.
• Strong written and verbal English; ability to work collaboratively across teams and geographies.

Nice-to-have:

• Experience with Cadence simulation and/or emulation products.
• Experience in memory sub-system or controller verification and operation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics, or Computer Science is preferred. Equivalent practical experience will be considered. (Source lists BS/MS in EE or CS and notes requirement for an Electrical, Electronics, or Computer Science engineering background.)

We seek engineers who deliver reliable verification solutions and mentor teams to improve verification practice.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.