Senior/Principal Signal Integrity Engineer — Silicon Photonics & AI Interconnects

Job Title

Senior/Principal Signal Integrity Engineer — Silicon Photonics & AI Interconnects

Role Summary

Lead signal integrity (SI) and related power-delivery engineering for advanced 2.5D/3D photonic-electronic packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory. Influence architecture from concept through production and work closely with silicon, photonics, packaging, and lab teams.

Work on high-speed electrical-optical interconnects for AI-scale computing and production-ready hardware.

Experience Level

Senior / Principal level. Typical requirement: 10+ years of relevant SI/PI experience in high-speed and package-level design and validation.

Responsibilities

Accountable for end-to-end SI analysis, optimization, and validation across advanced packaging and hybrid electrical-optical systems.

• Perform EM modeling, extraction, and simulation of advanced packages (silicon interposers, bridges, 2.5D/3D stacks, fan-out, CoWoS-/EMIB-like structures).
• Conduct end-to-end high-speed channel analysis for analog circuits, SerDes (PAM4/NRZ at 100G+/lane), parallel buses, UCIe die-to-die links, and hybrid electrical-optical interconnects.
• Develop and optimize package stack-ups, routing strategies, via transitions, bump pitch/layout, and redistribution layers to minimize insertion/return loss, crosstalk, mode conversion, and impedance discontinuities.
• Collaborate on bump map/pinout optimization, die-to-package co-design, and floorplanning to meet SI targets across CMOS, BiCMOS, and photonic processes.
• Execute pre- and post-layout SI simulations with industry-standard tools and recommend mitigations (equalization, redundancy, material choices).
• Establish SI design rules, guidelines, and best practices for advanced photonic-integrated packaging.
• Partner with lab teams to correlate simulations with high-frequency measurements (VNA, TDR/TDT, oscilloscopes, BERTs), including de-embedding of fixtures and launches.
• Coordinate concurrent SI/PI analysis, addressing SSO, PDN resonance effects, and decap optimization.
• Lead technical reviews, present findings to cross-functional stakeholders, and drive timely closure of design issues.
• Advance methodology for emerging technologies such as optical interconnects, glass-core substrates, wafer-/panel-level packaging, and CPO/NPO architectures.

Requirements

Must-have technical skills, tools, and experience.

• 10+ years' experience in high-speed SI/PI with board-, package-, and silicon-level design/validation.
• Deep expertise in very high-speed SerDes (≥56G; preferably 100G/200G PAM4): channel modeling, equalization (FFE/DFE/CTLE), jitter/crosstalk analysis, eye/BER analysis, and compliance/margining.
• Extensive hands-on experience with SI/PI/EM tools (examples: Ansys HFSS 3D/Layout, SIwave, Clarity, CST, Keysight ADS/Momentum/Sigrity, HSPICE, HyperLynx).
• Proficiency in time-domain transient simulations and scripting/automation (HSPICE, ADS, MATLAB/Simulink, Python, TCL, MATLAB) for flows, data analysis, and reporting.
• Hands-on experience with 2.5D/3D packaging technologies (interposers, chiplet integration, HBM stacking) and high-frequency transmission-line routing in silicon/photonic contexts.
• Strong lab skills with high-bandwidth instruments, measurement-simulation correlation, fixture/probing design, de-embedding, and vendor lab management.
• Proven track record bringing complex high-speed hardware/optical modules from concept to production, including multiple design spins and volume manufacturing support.
• Demonstrated leadership in cross-functional design reviews and clear technical communication.

Nice-to-have:

• Experience with power integrity co-simulation and SSO in advanced photonic-electronic packages.
• Knowledge of emerging substrates (glass core, panel-level packaging) and optical interconnects (CPO/NPO).
• Background in EMI/EMC, mechanical, and thermal trade-offs for co-packaged optics.
• Familiarity with advanced nodes and chiplet standards (UCIe).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Physics, or a related field required; PhD preferred.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.