Senior Principal Physical Design Engineer (Austin Hiring Event)

Job Title

Senior Principal Physical Design Engineer (Austin Hiring Event)

Role Summary

Senior technical leader on the central physical design team responsible for RTL-to-GDSII implementation, methodology, and tooling for next-generation high-performance processor SoCs targeted at server and networking applications. The role combines hands-on technical ownership of back-end flow and signoff with strategic leadership of physical design capabilities.

Experience Level

Senior — leadership role. The posting expects extensive experience; typical candidates have 15+ years of progressive back-end physical design experience or equivalent professional experience.

Responsibilities

Lead technical and organizational activities to deliver complex SoC tapeouts and to advance physical design methodology and automation.

• Define long-term vision and infrastructure for physical design capabilities aligned to company technology strategy.
• Lead RTL-to-GDSII implementation across synthesis, floorplanning, power grid design, place & route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS).
• Provide strategic leadership and technical direction to physical design teams to ensure successful, timely tapeouts.
• Mentor and develop engineering talent; oversee team structure, hiring, performance management, and career development.
• Drive cross-functional collaboration to influence design decisions and resolve conflicts.
• Develop and deploy next-generation methodologies, flows, and automation to improve productivity and design quality.

Requirements

Core technical skills, hands-on EDA experience, and leadership track record are required; degree expectations are summarized separately below.

• Extensive experience in back-end physical design and verification with significant leadership roles and delivered SoC tapeouts.
• Proven ability to lead and scale physical design teams and manage complex projects under aggressive schedules.
• Deep expertise in hierarchical physical design strategies, ASIC design flow, RTL integration, synthesis, and timing closure.
• Practical experience with modern EDA tools and flows and with automation/scripting (Makefile, Tcl, Python, Perl).
• Strong communication and collaboration skills; ability to influence cross-functional teams and executive stakeholders.
• Nice-to-have: familiarity with static timing analysis tools (PrimeTime, Tempus), EM/IR tools (Voltus, Redhawk, PrimeRail), extraction tools (Quantus, StarRC), physical/formal verification tools (Formality, Verplex, Calibre, Hercules), and AI/ML-driven optimization in physical design tools.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related field with ~15+ years of related professional experience; or Master’s degree in Computer Science, Electrical Engineering or related field with ~10–12 years; or PhD in Computer Science, Electrical Engineering or related field with ~8–10 years; or equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.