Senior/Principal Physical Design Engineer

Job Title

Senior/Principal Physical Design Engineer

Role Summary

Implement end-to-end physical implementation of complex ASIC/SoC designs, from synthesis through sign-off, with opportunities for full‑chip ownership. Work closely with RTL, verification, DFT, and process teams to optimise performance, power, and area while ensuring manufacturability and yield.

Experience Level

Senior — 8+ years of experience in physical design for advanced technology nodes is preferred.

Responsibilities

Deliver physical design and sign‑off for high‑performance chips and collaborate across design and process teams.

• Drive floorplanning, placement, clock tree synthesis (CTS), routing, and sign‑off; potential full‑chip ownership.
• Perform synthesis, static timing analysis (STA), and timing optimization to meet PPA targets.
• Plan and analyse power, address IR drop and electromigration, and implement low‑power techniques and multi‑power domains.
• Ensure physical verification compliance (DRC, LVS) and support sign‑off flows.
• Integrate DFT structures and collaborate with DFT engineers during physical implementation.
• Develop and maintain EDA flows and automation for place & route, STA, and sign‑off.
• Interface with foundries and process engineers to address manufacturability and yield.
• Collaborate with RTL and architecture teams to drive physical‑aware RTL and constraints.
• Apply advanced tools and models (including AI‑based tools) to improve productivity and analysis.

Requirements

Core technical skills and experience required for success in this role.

• Must-have: Extensive experience in ASIC/SoC physical design, including P&R, CTS, routing, and sign‑off for advanced nodes.
• Must-have: Proficiency with EDA tools for place & route and STA; ability to develop flows and automation.
• Must-have: Strong skills in timing closure, signal integrity analysis, and IR drop analysis.
• Must-have: Proficiency in scripting for automation (TCL, Python, Perl, or similar).
• Must-have: Practical knowledge of CMOS technology and semiconductor process limitations.
• Nice-to-have: Experience with AI accelerators, HPC or networking chips, and foundry interactions.
• Nice-to-have: Experience leveraging advanced AI tools within engineering workflows.
• Other: Strong problem‑solving, communication, and teamwork in collaborative environments.
• Compliance: Role may require export‑control eligibility checks and related clearances.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Fractile

Headquarters: London, UK

Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.