Senior Principal PCIe PHY Signal & Power Integrity Engineer

Job Title

Senior Principal PCIe PHY Signal & Power Integrity Engineer

Role Summary

Lead electrical validation, compliance readiness, and system-level debug for high-speed PCIe PHY interfaces used in storage accelerator and high-performance platform designs. Work cross-functionally with silicon design, firmware, board design, SI/PI, manufacturing, and customers to ensure performance, robustness, and compliance from pre-silicon through production.

Hands-on role focused on lab characterization, compliance preparation, link-level debugging, and production support for PCIe Gen5/Gen6 and related form factors (HHHL, OCP, EDSFF).

Experience Level

Senior-level (Principal). The role expects extensive, senior technical experience in PCIe PHY/SerDes validation and board-level bring-up.

Responsibilities

Primary responsibilities include defining and executing PCIe PHY validation strategy, hands-on electrical characterization, and cross-functional debug from silicon bring-up to production readiness.

• Own PCIe PHY validation strategy and define lab tests, pass/fail criteria, and DVT/PVT coverage.
• Plan and execute electrical characterization of transmitter/receiver, clocks, reset, equalization, and margining using oscilloscopes, BERTs, VNAs/TDRs, pattern generators, and protocol analyzers.
• Analyze eye diagrams, jitter, CTLE/DFE behavior, de-emphasis, insertion/return loss, and crosstalk under realistic system conditions.
• Use modeling and simulation to predict system performance and guide board/package design for first-pass success.
• Debug link training and stability (LTSSM), firmware/register interactions, retimer/redriver, connector/cable, and platform-level contributors to failures.
• Prepare products for external compliance and interoperability testing; work with internal/external labs and partners to close gaps.
• Support manufacturing (FCT/ICT), RMA analysis, and customer-facing debug during ramps.
• Mentor engineers, review validation plans/results, and present technical recommendations to leadership.

Requirements

Must-have technical skills and experience required for successful performance in this role. Preferred skills follow.

• Must-have: Extensive hands-on experience validating PCIe PHYs or high-speed SerDes interfaces at silicon, board, or system level.
• Must-have: Practical lab expertise with high-bandwidth oscilloscopes, BERTs, protocol analyzers, compliance software, pattern generators, VNAs/TDRs, differential probes, and precision clock/jitter measurement tools.
• Must-have: Deep knowledge of PCIe electrical concepts: eye margin, jitter decomposition, transmitter presets, receiver equalization, CTLE, DFE, de-emphasis, SSC, and compliance masks.
• Must-have: Ability to debug interactions across PHY settings, firmware, BIOS, host platforms, add-in cards, retimers/redrivers, connectors, cables, board layout, power delivery, and thermal conditions.
• Must-have: Strong data analysis and automation skills (Python, instrument APIs, register/scripts, log parsing, structured reporting).
• Preferred: High-speed channel modeling experience (S-parameters, insertion/return loss) and correlation of simulation to measurement.
• Preferred: Linux-based bring-up experience, low-level register debug, firmware-controlled PHY tuning, and production validation flows.
• Preferred: SI/PI background and PCB/package layout experience (Cadence Allegro, APD, or similar); familiarity with IC floor planning, EM/IR analysis, and co-design methodologies.

Education Requirements

The posting references engineering degrees generally and notes employees include Master's and Ph.D. graduates. No explicit minimum degree, specific degree type, or field-of-study requirement is stated in the job text.

About the Company

Company: MaxLinear

Headquarters: Carlsbad, CA, United States

Fabless semiconductor company that designs RF, analog, digital, and mixed-signal system-on-chip solutions for access and connectivity, data center and optical interconnects, wired/wireless infrastructure, and industrial and multi-market applications.