Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

Job Title

Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

Role Summary

Drive layout-driven pathfinding and architecture exploration for next-generation memory modules and form factors (DDR6, LPDDR6/LPDDR7, MRDIMM Gen3/Gen4, SOCAMM2 and beyond). Work within the Module Architecture Group on pre-product definition, feasibility studies, and design trade-off analysis to influence module architecture through physical-layout insights.

Experience Level

Senior / Principal level — typically 8–15+ years of experience in high-speed PCB/layout engineering, signal integrity, and architecture-level pathfinding.

Responsibilities

Key responsibilities include technical leadership of layout-driven exploration, collaboration with SI/PI teams, and development of manufacturable design rules.

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
• Evaluate form factor, routing topology, and pinout trade-offs to meet bandwidth and density targets.
• Define feasible design envelopes: routing complexity, layer count, escape feasibility, and via strategy.
• Collaborate with SI/PI teams to co-optimize channel topology, loss/reflection mitigation, crosstalk control, and return path integrity.
• Define and influence SI/PI budgets and translate electrical budgets into physical layout constraints.
• Drive adoption and evaluation of advanced PCB technologies (ultra-low-loss materials, HDI, stacked/microvias, via-in-pad) and advanced packaging integration where applicable.
• Develop next-generation layout methodologies, routing rules for >10–20+ Gb/s signaling, and reference design guidelines.
• Establish and document design rules that bridge architecture → SI/PI → layout → manufacturing; conduct design reviews and risk/trade-off analyses.
• Provide practical layout input to industry standards and mentor junior engineers to shape organization-wide layout practices.

Requirements

Must-have technical skills and experience for this role.

• 8–15+ years of experience in high-speed PCB layout with ownership of complex designs and module-level pathfinding.
• Deep experience with DDR/LPDDR or similar ultra-high-speed parallel interfaces.
• Strong expertise in signal integrity (transmission lines, discontinuities, channel loss mechanisms) and power integrity (PDN design, target impedance, decoupling optimization).
• Advanced proficiency with Cadence Allegro / OrCAD or equivalent high-end PCB layout tools.
• Proven ability to influence architecture decisions using physical design constraints and modeling-informed trade-offs.
• Experience in cross-functional architecture or pathfinding environments and conducting trade-off analyses.
• Familiarity with advanced PCB/packaging technologies and ability to assess manufacturability implications.
• Proficient in using AI tools in daily engineering work.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is specified. The posting does not require a specific advanced degree or certifications; it emphasizes extensive practical experience (8–15+ years) in high-speed layout and SI/PI work.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.