Senior Principal Interface IP Verification Engineer (Pre-Silicon)
Lead pre-silicon verification of high-speed Interface IP (PCIe, CXL, DDR, Ethernet). Design and maintain scalable UVM/SystemVerilog verification environments, define verification strategies, and ensure product quality and performance through collaboration with architects, RTL, firmware, and systems teams.
Work on a team responsible for Interface IP used in AI accelerators, data centers, networking platforms, and SoCs.
Senior β typically 8β10+ years of direct industry ASIC/SoC verification experience.
Key responsibilities include:
Must-have and preferred qualifications.
Bachelor of Science in Electrical Engineering (BSEE) is specified; the posting also expects 8β10+ years of industry ASIC/SoC verification experience.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
