Senior Principal Hardware Engineer

Job Title

Senior Principal Hardware Engineer

Role Summary

Lead physical design engineering for Cadence's emulation-acceleration systems. The role focuses on driving solutions across synthesis, floorplanning, placement & routing, clock construction, and signoff to achieve tape-out for complex HPC devices.

This position is on the core technology team and requires collaboration with RTL, DFT, architecture, and R&D groups. Location: US offices (San Jose, CA or Cary/Raleigh, NC).

Experience Level

Senior (principal) level. Typical candidates will have substantial hands-on industry experience; this is a senior engineering role with multi-year experience expectations.

Responsibilities

Primary responsibilities include:

• Drive physical-design solutions across logic synthesis, floorplan, placement and routing, and clock construction.
• Deliver design closure for timing, power, IR/EM, and foundry signoff requirements.
• Optimize power, performance, and area to meet product constraints.
• Collaborate with RTL, DFT, architecture, and cross-functional teams to ensure correct execution.
• Provide continuous improvement to tools, flows, and methodologies and work with R&D to enhance Cadence tool suites.
• Lead or own blocks/SoCs through tape-out activities.

Requirements

Must-have technical skills and traits:

• Deep knowledge of floorplanning, placement & routing, timing analysis, and physical verification.
• Experience with signoff closure related to timing, power, IR/EM, and foundry rules.
• Familiarity with advanced process nodes and associated implementation challenges.
• Proven ability to collaborate across disciplines and communicate technical issues clearly.
• Experience improving or contributing to EDA tools, flows, or automation.
• Proficiency in at least one scripting language is preferred (Perl, Python, Tcl, Shell).
• Self-motivated, strong problem-solving skills, and track record of delivering results in complex projects.

Education Requirements

Degree and experience combinations specified in the posting: BS with a minimum of 10 years of relevant experience, MS with a minimum of 7 years, or PhD with a minimum of 5 years. The posting also references BS/MS candidates with ~8–15+ years of hands-on physical-design experience. Equivalent practical experience was presented as the basis for these experience thresholds.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.