Senior Principal Engineer – Switch Architecture
Marvell TechnologyJob Title
Senior Principal Engineer – Switch Architecture
Role Summary
Join the Teralynx Switch Architecture team to define architecture, behavioral models, and performance analysis for Marvell's next-generation data center switch ASICs. The role leads cross-functional technical efforts from concept through silicon and production.
Experience Level
Senior role. Typical experience expectation: 15+ years of relevant semiconductor or ASIC architecture experience (or 10–12+ years with an advanced degree).
Responsibilities
The role leads architecture definition and validation for high-performance switch ASICs. Key responsibilities include:
- Define features, pipelines, protocols, and micro-architecture for next-generation data center switch chips.
- Develop behavioral and performance models to validate architectural decisions and ensure scalability.
- Drive end-to-end architecture from high-level concept through implementation, verification, and silicon bring-up.
- Analyze trade-offs across latency, throughput, memory architecture, power, area, and QoS.
- Collaborate with ASIC design, software, SerDes, firmware, validation, systems engineering, and product teams.
- Participate in customer-facing technical discussions and align product capabilities to use cases.
- Mentor engineers and promote architectural best practices across the organization.
Requirements
Must-have technical skills and experience:
- Proven track record architecting complex ASICs, preferably in networking or switch domains.
- Expertise in behavioral and performance modeling and architecture validation at system level.
- Strong programming skills in C/C++ and Python for modeling and tooling.
- Experience driving cross-functional engineering projects and collaborating across geographies.
- Excellent verbal and written communication skills for explaining complex architectural concepts.
- Ability to evaluate system-level tradeoffs (latency, throughput, memory, power, area, QoS).
- May require export-control eligibility; candidates not U.S. citizens or permanent residents may be subject to export license review prior to employment.
Nice-to-have:
- Experience with multi-die / chiplet architectures, die-to-die interfaces, or advanced packaging.
- Familiarity with switch pipeline architectures, buffer management, traffic engineering, and programmable datapaths.
- Customer or standards-body engagement experience; publications, patents, or prior architecture leadership roles.
Education Requirements
Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 15+ years of relevant experience; or Master’s/PhD with approximately 10–12+ years of relevant semiconductor architecture or ASIC development experience. Equivalent practical experience may be considered where explicitly stated by the employer.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
