Senior Principal Engineer / Subject Matter Expert, Quartus Timing Analysis & Optimization

Job Title

Senior Principal Engineer / Subject Matter Expert, Quartus Timing Analysis & Optimization

Role Summary

Lead the architecture, development, and advancement of timing analysis, modeling, and optimization technologies within the Quartus FPGA Compiler. Provide technical leadership across compilation, synthesis, fitting, routing, and timing teams to improve timing QoR, runtime, scalability, and signoff correlation.

Experience Level

Senior — 15+ years of relevant experience (EDA software development, timing analysis, physical design, or FPGA compilation).

Responsibilities

Deliver technical direction and implement high-performance timing and optimization engines for the Quartus compilation flow.

• Define and drive the technical roadmap for timing analysis, modeling, and optimization.
• Architect and implement next-generation STA capabilities (graph- and path-based analysis) and support complex scenarios such as MCMM, timing exceptions, CDC, variation-aware methods, and incremental analysis.
• Develop timing modeling and signoff correlation methodologies that align Quartus results with silicon behavior.
• Design scalable compiler data structures and algorithms; improve performance via parallelization, multi-threading, and incremental processing.
• Improve timing convergence and QoR across RTL-to-bitstream flows through timing-driven optimizations.
• Provide cross-functional technical leadership, mentoring, and collaboration with synthesis, placement, routing, architecture, verification, and software teams.

Requirements

Must-have technical skills, experience, and eligibility requirements. Preferred items listed separately.

• 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
• Deep expertise in static timing analysis (STA), timing closure methodologies, timing modeling and correlation, physical design optimization, RTL-to-GDS/bitstream flows, and MCMM analysis.
• Strong understanding of placement and routing algorithms, clock analysis and optimization, path-based analysis (PBA), constraint management, timing exceptions, and incremental timing architectures.
• Extensive software development experience in C++ and building large-scale optimization systems; experience with multi-threaded or distributed infrastructure.
• Proven track record developing high-performance, highly scalable EDA engines and shipping production tools.
• Applicants must be eligible for any required U.S. export authorizations.

Nice-to-have

• Direct experience developing FPGA compilation tools or with the Quartus compiler, Timing Analyzer, Fitter, or Router.
• Expertise in path-based timing optimization, CRPR, latch-based timing analysis, incremental optimization frameworks, timing-driven placement/routing, or variation-aware techniques.
• Industry-recognized technical leadership such as patents, publications, standards contributions, or major product innovations.

Education Requirements

MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.