Senior Principal Engineer - SoC/Chip Lead

Job Title

Senior Principal Engineer - SoC/Chip Lead

Role Summary

Lead technical execution for complex SoC programs from architecture through silicon production. Serve as the chip-level technical owner, coordinating cross-functional teams (digital, verification, physical design, DFT, firmware, validation, packaging, product engineering) to deliver advanced-node ASIC/SoC products.

Experience Level

Senior — experienced technical leader. Requires extensive semiconductor industry experience (20+ years indicated).

Responsibilities

Accountable for end-to-end SoC delivery and technical leadership across multiple domains.

• Own technical leadership and execution from architecture through silicon production and productization.
• Define chip-level architecture, integration requirements, performance, power, and area targets.
• Drive integration strategy, tape-out readiness, schedules, risk management, and trade-off analyses.
• Coordinate and lead cross-functional design, verification, physical design, DFT, firmware, validation, packaging, and product teams.
• Oversee subsystem and IP integration, including multi-domain SoC components.
• Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems.
• Conduct design reviews, execution reviews, silicon readiness assessments, and post-silicon debug.
• Drive issue resolution throughout development to achieve first-pass silicon success.
• Mentor senior engineers and provide technical leadership across organizations.

Requirements

Must-have technical background and leadership experience; preferred items listed separately.

• 20+ years semiconductor industry experience with substantial leadership responsibility.
• Proven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent for large-scale ASIC/SoC products.
• Deep understanding of SoC architecture, integration methodologies, and full-chip development flows.
• Strong experience across RTL design, design verification, physical design, DFT, static timing analysis, low-power design methodologies, silicon bring-up, and productization.
• Experience managing complex schedules, technical dependencies, and cross-functional execution across global teams.
• Strong communication, stakeholder management, and engineering leadership skills.
• Preferred: experience leading advanced-node SoCs (3nm and/or 5nm) and working with high-speed SerDes, mixed-signal IP, and advanced PHYs.
• Preferred: exposure to NoC architectures, data movement/interconnect fabrics, high-bandwidth memory systems, multi-die/chiplet architectures, packaging and signal integrity for high-speed systems, and domains such as AI/HPC/networking/data-center.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline (explicitly listed in the source).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.