Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture
SiFiveJob Title
Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture
Role Summary
Lead the physical-design methodology and RTL-to-GDS architecture for next-generation, high-frequency CPU cores. This is a cross-functional technical leadership role responsible for defining methodology roadmaps, influencing micro-architectural trade-offs, and driving automation and AI/ML integration across the physical implementation flow.
Work closely with CPU architects, RTL teams, EDA vendors, IP and foundry partners to deliver predictable, high-performance tape-outs at sub-3nm process nodes.
Experience Level
Senior — requires extensive industry experience; the posting specifies 15+ years in Physical Design and Methodology with proven tape-out leadership.
Responsibilities
Provide technical leadership and define the global methodology for physical implementation of ultra-high-frequency CPUs.
- Architect and validate RTL-to-GDS roadmaps tailored for ultra-high-frequency CPU designs.
- Influence early-stage micro-architectural decisions through PPA modeling and physical feasibility studies.
- Drive AI/ML-based EDA transformation and scale ML-driven optimization platforms across flows.
- Act as the primary technical interface to tier-one EDA, IP, and foundry partners to influence tool and library roadmaps.
- Define global floorplanning, timing budgets, and integration strategies for large hierarchical designs to ensure convergence.
- Establish scalable, reproducible flows-as-code, telemetry, and automated build systems for predictable execution.
- Mentor and elevate Principal and Senior engineers across the physical design organization.
Requirements
Key must-have skills and experience for immediate contribution; follow-on items are nice-to-have.
- Must-have: 15+ years of hands-on experience in Physical Design and Methodology with leadership on high-speed CPU tape-outs (3GHz+).
- Must-have: Direct, hands-on tape-out experience with TSMC N3 process node.
- Must-have: Expert-level proficiency with Synopsys Fusion toolset (Fusion Compiler, ICC II, PrimeTime) and ability to debug core algorithmic behavior.
- Must-have: Demonstrated deployment of ML-based design-space optimization tools in production to achieve measurable PPA improvements.
- Must-have: Strong software automation skills (Python, Tcl, or Perl) and experience building scalable flows and automation frameworks.
- Must-have: Deep technical expertise in device physics impacts at sub-3nm (timing closure at low voltages, IR drop, EM, crosstalk) and practical mitigation strategies.
- Must-have: Proven ability to lead cross-functional integration with architects, RTL teams, EDA vendors, IP and foundry partners.
- Must-have: Authorization to work in India and ability to pass background/reference checks and any required export-control clearances.
- Nice-to-have: Exposure to N2/A14 generation nodes; experience with DSO.ai, Cerebrus, or similar ML EDA platforms.
- Nice-to-have: Experience co-optimizing standard cell and SRAM library architectures for PPA extraction and custom EDA feature requests.
Education Requirements
Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related highly technical field (as stated in the posting).
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
