Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Job Title

Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Role Summary

Technical lead responsible for end-to-end hardware ownership of Optical DSP (ODSP) chip programs within the Connectivity Business Unit. Lead cross-functional multi-site teams through architecture, design, tape-out, bring-up, validation, and production release.

Primary mission: deliver complex mixed-signal SoC/ASIC products (high-speed SerDes, DSP datapath, analog/digital integration) on advanced CMOS nodes while managing schedule, risk, and technical quality.

Experience Level

Senior — senior individual contributor/technical leader. Typical experience: Bachelor's +15 years, Master’s +10–12 years, or PhD +8–10 years (see Education Requirements for details).

Responsibilities

The role combines program leadership, technical direction, and hands-on execution across the full chip lifecycle.

• Serve as primary hardware technical owner for an ODSP chip program from POR through MPR, representing hardware at program milestones.
• Finalize PRD and bring-up requirements in collaboration with architecture, marketing, and applications teams.
• Coordinate and align cross-functional teams (analog, digital, DV, DFT, PD, STA, firmware, validation, ATE/test, product engineering, quality).
• Define high-level technical solutions and set technical direction across mixed-signal integration, SerDes, DSP datapath, and SoC architecture.
• Identify technical risks early and drive mitigation across functional teams; report status and risks to BU leadership.
• Lead end-to-end chip design execution on advanced CMOS nodes (TSMC 2nm/3nm/5nm), including RTL, physical design, DFT, timing closure, and tape-out.
• Own chip bring-up plan and execution, drive Phase 0/1/2 bring-up through silicon validation and production release.
• Oversee silicon validation, PVT characterization, ATE test program development, qualification (ESD, LU, HTOL), and post-silicon issue resolution.
• Mentor and develop engineering talent; promote knowledge sharing and continuous improvement in design methodology and flows.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs through tape-out and productization.
• Deep expertise in high-speed mixed-signal SoC design: SerDes (100G+/lane), DSP datapath, and analog/digital integration.
• Strong understanding of full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out.
• Experience with advanced CMOS process nodes (5nm, 3nm; role references 2nm/3nm/5nm design targets).
• Experience leading and coordinating cross-functional hardware teams across global, multi-site organizations.
• Demonstrated ability to drive silicon bring-up, debug, validation, and production release; experience with ATE test program development and silicon characterization.
• Excellent communication and stakeholder engagement skills; able to present technical status and risks to BU leadership.
• Highly motivated, self-driven, and effective in ambiguous, fast-paced, multi-program environments.

Nice-to-have:

• Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products.
• Experience with eAVS or other power-optimization subsystems, SiPho integration, or module-level validation.

Education Requirements

One of the following is expected: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years' experience; OR Master's degree in Electrical Engineering, Computer Engineering, or related field with 10–12 years' experience; OR PhD in Electrical Engineering, Computer Engineering, or related field with 8–10 years' experience. Related technical fields are acceptable where accompanied by equivalent industry experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.