Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Job Title

Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Role Summary

Senior individual contributor in Marvell's U.S. Customer Solutions Group responsible for ensuring customer platforms using Marvell Ethernet switch and UALink silicon meet production-grade signal integrity (SI) and power integrity (PI) requirements from prototype through mass production. Works directly with customers, ODMs, and internal silicon, packaging, and hardware teams to define guidelines, validate designs, and drive corrective actions.

Experience Level

Senior — typical candidate has 15+ years of hardware design, validation, and SI/PI experience; the posting notes that exceptionally strong candidates with fewer years but demonstrable mastery will be considered.

Responsibilities

Primary technical responsibilities and customer-facing activities.

• Act as senior SI/PI authority for customer platforms built on Marvell Ethernet and UALink silicon from early channel definition through production qualification.
• Define and maintain layout, routing, and stack-up guidelines for high-speed SerDes channels and PDNs; drive adoption with customers, ODMs, and internal teams.
• Perform post-silicon channel extraction, full-channel simulation, what-if analysis, and recommend layout/stack-up fixes to improve margins.
• Lead compliance testing and lab characterization (BER/SER, eye margin, jitter, return loss, crosstalk) and convert measurements into actionable design and SerDes-tuning guidance.
• Run and review PDN/PI simulations (impedance, IR drop, decoupling, transient response, droop) and guide customers on robust PDN architectures.
• Provide SerDes tuning guidance and correlate simulation, lab, and field telemetry with Marvell silicon teams to refine methodologies.
• Engage with ODMs on design reviews and qualification, support reference design SI/PI definition, and provide hands-on lab debug during bring-up and production ramp.
• Develop and deliver SI/PI training for customers, ODMs, and internal teams; represent Marvell in customer briefings and technical forums.
• Contribute SI/PI input to product definition and roadmap planning and champion improvements back into silicon, packaging, and platform engineering.

Requirements

Must-have skills and experience (preferred items listed separately).

• 15+ years in hardware design, development, and validation of high-speed networking or compute systems (typical expectation for this role).
• 10+ years focused on signal integrity and power integrity for high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).
• Demonstrated expertise across the SI lifecycle: channel modeling/budgeting, layout/stack-up guideline definition, post-layout extraction and simulation, design fixes, and compliance/tuning guidance.
• Strong PI capability: ability to run/review PDN simulations and translate results into customer guidance on decoupling, IR drop, and transient response.
• Fluency with SI/PI EDA toolchains (e.g., Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI) and willingness to use the tools required by a project.
• Hands-on lab expertise with VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and high-speed compliance test kits; proven debug capability in lab and customer environments.
• Customer-facing experience supporting complex technical engagements and resolving deployment issues; strong communication and influence skills.
• Eligibility to access export-controlled technology and willingness to undergo export license review if required.
• Preferred:
  • Experience with Ethernet switch platforms and/or emerging open AI fabric standards.
  • Experience supporting SI/PI for megascale data center platforms at production volume and familiarity with ODM/CM flows, reliability testing, and manufacturing variability.
  • Experience defining SerDes tuning methodologies and familiarity with chip-to-module, copper cable, and connector ecosystems.

Education Requirements

PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related technical field is listed as the expected education.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.