Senior Principal Engineer - DFT

Job Title

Senior Principal Engineer - DFT

Role Summary

Lead DFT architect and technical owner for complex mixed-signal SoCs in Marvell's Optical DSP organization. The role defines and implements DFT/DFX features, validates IP and system-level test flows, and drives post-silicon bring-up and debug across multiple generations.

Work with global cross-functional teams and mentor a team of DFT engineers to scale DFT methodology, tools, and execution for advanced-process-node ASIC programs. Base pay range: USD 182,360–273,200 per year.

Experience Level

Senior - this role expects experienced individual contributor/technical leader level. The posting specifies typically 13+ years of related experience (15+ years with a Bachelor's; 13+ years with an advanced degree).

Responsibilities

Primary responsibilities include technical leadership, DFT architecture, implementation, and validation.

• Architect and define DFT and test methodologies for mixed-signal SoCs across multiple generations.
• Implement DFT/DFX features (scan, MBIST, IP-DFT) and integrate with design flows.
• Lead validation, static timing-aware test planning (STA), pattern generation, and post-silicon bring-up and debug.
• Mentor, guide, and grow a team of DFT engineers; drive team execution across multiple designs.
• Develop and enhance DFT methodologies and tool flows; benchmark and enable new DFT approaches.
• Collaborate with design, verification, IP, and post-silicon teams to ensure testability and product readiness.

Requirements

Must-have technical skills and relevant hands-on experience.

• Hands-on experience across DFT execution stages: SCAN, MBIST, validation, STA, IP-DFX, and post-silicon bring-up/debug.
• Proven involvement in DFT architecture definition for multiple designs.
• Strong fundamentals in digital circuit and logic design.
• Experience with industry EDA toolsets (Cadence / Mentor / Synopsys): examples include Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax.
• Ability to lead technical teams and mentor engineers.
• ASIC design experience is a plus.
• Scripting skills (Python, Perl, Tcl, C-Shell) are a plus.
• May require eligibility to access export-controlled technology; candidates may be subject to export-license review.

Education Requirements

Posting specifies: Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 15+ years of related professional experience; or a Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related field with 13+ years of experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.