Senior Principal Engineer, Design Verification

Job Title

Senior Principal Engineer, Design Verification

Role Summary

Lead architecture and delivery of functional verification environments and strategies for complex SoC designs in the Data Center domain. The role focuses on SystemVerilog/UVM testbench development, coverage-driven verification, debug, and driving verification methodology and productivity improvements across teams.

Experience Level

Senior — role expects an experienced verification lead. The posting lists degree/experience combinations (Bachelor's +15 years; Masters +10 years; PhD +8 years); typical candidates have 10+ years of verification experience.

Responsibilities

Primary responsibilities include design verification architecture, test development, and technical leadership:

• Design and implement verification environments, reference models, bus-functional monitors and drivers using SystemVerilog and UVM.
• Analyze designs and architectures to develop verification strategies and detailed verification testplans.
• Write and execute randomized tests and coverage-driven verification; measure and improve coverage.
• Debug failures, diagnose root causes, and collaborate with designers to resolve issues.
• Drive SoC-level verification methodology, tools, and automation to improve productivity and quality.
• Provide technical leadership and mentorship to geographically dispersed verification teams.
• Independently propose and define high-level technical work and verification objectives.

Requirements

Must-have skills and experience (concise):

• Proven architecture and implementation experience with complex/random verification environments using SystemVerilog and UVM.
• Extensive hands-on verification experience at block, subsystem, and full-chip levels.
• Technical leadership experience driving multi-domain SoC verification efforts and cross-functional collaboration.
• Experience developing and executing detailed verification testplans and coverage analysis.
• Proficiency with scripting (Python or Perl), EDA verification tools, bug tracking, and regression systems.
• Ability to analyze verification data, prioritize work, multitask in a fast-paced environment, and mentor technical teams.

Education Requirements

Options stated in the posting: Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering or related field with 15+ years of experience; Masters degree and/or PhD in those fields with 10+ years of experience; PhD with 8+ years of experience. The posting references related technical fields for degree background.

Additional Information

Expected base pay range (USD): 204,900 - 303,250 per annum. Marvell provides standard employee benefits and is an equal opportunity employer. Applicants who require a reasonable accommodation during the selection process may contact Marvell HR Helpdesk at TAOps@marvell.com for assistance.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.