Senior Principal Engineer — ASIC Silicon Debug, Device Technology & Yield Engineering

Job Title

Senior Principal Engineer — ASIC Silicon Debug, Device Technology & Yield Engineering

Role Summary

Lead post-silicon debug, failure analysis, and yield improvement activities for advanced ASIC products within Device Technology & Yield Engineering. Work cross-functionally with design, foundry, test, quality, and product teams to identify root causes and implement corrective and preventive actions.

Experience Level

Senior — expects 12+ years of semiconductor industry experience, including leadership of yield, RMA, or failure analysis programs.

Responsibilities

Accountable for end-to-end post-silicon investigations, technical leadership, and communicating findings to stakeholders.

• Lead root-cause analysis of silicon yield loss, field returns, customer escalations, and reliability failures.
• Define hypothesis-driven debug strategies and coordinate cross-functional execution across design, DFT, test, package, foundry, and operations.
• Analyze device- and circuit-level failure mechanisms and process sensitivities affecting ASIC functionality and yield.
• Drive advanced failure analysis (FIB, SEM/TEM, EFA, OBIRCH, LVP, emission microscopy, cross-section) and interpret results into engineering actions.
• Develop silicon characterization plans to isolate process, design, and test contributors and translate findings into design and process improvements.
• Present technical findings and remediation plans to executive leadership and coordinate containment, corrective actions, and prevention plans.

Requirements

Must-have technical skills and experience required to perform the role; preferred skills that improve candidacy are listed separately.

• Must-have: 12+ years in the semiconductor industry with demonstrated success leading yield improvement, RMA, and failure-analysis efforts.
• Must-have: Deep understanding of CMOS device physics, advanced process technologies, and process-design interaction analysis.
• Must-have: Strong expertise in SRAM architecture and memory failure mechanisms, and experience with high-speed interfaces (PCIe, ONFI, SerDes) and related debug.
• Must-have: Hands-on post-silicon debug and characterization experience and familiarity correlating WAT, electrical test, yield, reliability, FA, and customer-return data.
• Must-have: Experience working directly with foundries and OSAT/external partners and driving multi-site technical investigations.
• Preferred: Background supporting SSD controller, AI accelerator, networking, or HPC ASICs; experience using AI/ML for yield analytics and RCA acceleration.
• Preferred: Proven track record resolving customer-visible field-quality issues and mentoring engineering teams.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.