Senior Principal Engineer, AI/ML

Job Title

Senior Principal Engineer, AI/ML

Role Summary

Lead RTL microarchitecture and implementation of an AI-enabled RISC-V CPU core and associated matrix/vector engines. Join the CPU/IP design team to define architecture, drive RTL development, and collaborate with verification and physical-design teams to meet performance, power, area, and timing targets.

Onsite positions available in Santa Clara, Richardson, and Austin; role reports to the CPU/IP engineering organization within the MIPS team.

Experience Level

Senior level — requires extensive microarchitecture and CPU implementation experience (senior/architect level). Specific experience guidance appears below in Education Requirements.

Responsibilities

Design, specify, and deliver CPU microarchitecture and RTL for AI-enabled RISC-V vector and matrix engines. Collaborate across teams to validate functional and physical implementation targets.

• Drive microarchitecture and RTL design for critical CPU core blocks.
• Design RISC-V vector CPU core and custom extensions; design matrix engine to augment vector units.
• Perform architectural exploration, microarchitectural research, and produce detailed specifications.
• Configure and refine design features to meet power, performance, area, and timing goals.
• Support functional verification and contribute to verification strategy and performance verification.
• Work with modeling, verification, and physical-design teams on timing, area, reliability, testability, and power integration.
• Follow Environmental, Health, Safety & Security requirements in all activities.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Hands-on knowledge of CPU pipeline stages for in-order or out-of-order high-performance cores.
• Deep understanding of microprocessor architecture: instruction fetch/decode, branch prediction, scheduling, register renaming, ROB, out-of-order execution, integer and FP execution, load/store pipelines, and prefetch mechanisms.
• Experience with vector datapaths, cache and memory subsystem design, and cache coherency/memory consistency models.
• Proficiency in SystemVerilog, Verilog and/or VHDL and RTL development practices.
• Experience using simulators and waveform/debugging tools for RTL and microarchitecture verification.
• Solid knowledge of logic design principles and understanding of timing and power implications.

Nice-to-have:

• Experience designing RISC-V, ARM, and/or MIPS CPUs, and familiarity with vector/matrix-enabled processors.
• Knowledge of hardware multithreading, virtualization, SIMD, low-power microarchitecture techniques, and SoC integration.
• Experience with scripting (Perl, Python) and an understanding of safety and security microarchitecture.

Education Requirements

Master's degree with 10+ years of relevant experience preferred; PhD with 5+ years of relevant experience also acceptable. (Degrees and years are stated as the target qualification levels in the source.)

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.