Senior Principal / Distinguished Engineer – SerDes Analog/Mixed-Signal Design

Job Title

Senior Principal / Distinguished Engineer – SerDes Analog/Mixed-Signal Design

Role Summary

Lead the design and delivery of high-speed analog and mixed-signal circuits and SerDes IP for next-generation AI infrastructure. Collaborate across architecture, digital design, layout, and validation to meet aggressive performance, power, and robustness targets.

Influence technical direction, resolve critical circuit-level problems, and drive designs from architecture through silicon validation.

Experience Level

Senior - principal/distinguished engineering level. Significant prior experience in high-speed analog/mixed-signal IC design is expected.

Responsibilities

Key responsibilities include technical leadership, circuit design, and ensuring silicon-quality delivery.

• Lead design and implementation of complex high-speed analog/mixed-signal circuits and critical SerDes IP.
• Define circuit approaches and methodologies to achieve performance, power, area, and robustness targets for 100G+ SerDes PHYs.
• Resolve challenging circuit-design issues through analysis, modeling, simulation, and silicon investigation.
• Lead technical reviews and influence decisions across architecture, analog/mixed-signal design, digital design, layout, physical design, and validation.
• Drive design closure including post-layout verification, performance optimization, and silicon correlation.
• Identify opportunities for architectural innovation, design automation, and improved engineering efficiency.
• Contribute to technical roadmaps, project planning, and risk mitigation for next-generation SerDes products.

Requirements

Required skills and experience, with preferred items noted.

• Must-have: Extensive experience in analog/mixed-signal IC design and advanced semiconductor product development, including 100G+ high-speed circuit design.
• Must-have: Demonstrated record of delivering complex circuit designs from architecture through implementation and silicon validation.
• Must-have: Strong debugging skills and ability to solve ambiguous, cross-disciplinary technical problems.
• Must-have: Excellent technical communication and ability to influence engineering decisions across teams.
• Nice-to-have: Significant experience developing 100G+ SerDes or other high-performance analog/mixed-signal IP.
• Nice-to-have: Expertise in advanced CMOS process technologies, circuit modeling, simulation automation, and silicon-to-model correlation.
• Nice-to-have: Hands-on experience with PLLs, LC-VCOs, DTC/TDC, phase interpolators, high-speed DACs, TIAs, CTLE, SAR ADCs, bandgaps, LDOs, charge pumps, and related analog blocks.
• Nice-to-have: Patents, technical publications, or other evidence of technical innovation.

Education Requirements

M.S. or Ph.D. in Electrical Engineering or a related field (as stated in the posting).

About the Company

Company: Upscale

Upscale builds high-performance infrastructure for AI, focusing on silicon, systems, and networking to support demanding AI workloads. Backed by significant funding, the company develops advanced SerDes and mixed-signal technologies for data centers and emphasizes engineering rigor, rapid execution, and impact.