Senior Principal DFT Design Engineer

Job Title

Senior Principal DFT Design Engineer

Role Summary

Lead and execute Design-for-Test (DFT) activities for complex SoC/ASIC projects, focusing on scan insertion, compression technologies, MBIST, and ATPG to meet test coverage and quality targets. Work with architecture, design, verification, and external customers to deliver production-ready test solutions.

Experience Level

Senior-level. Prior 10–20 years of professional experience in SoC/ASIC digital design with a focus on DFT is expected.

Responsibilities

Primary responsibilities include DFT implementation, test pattern generation, and post-ATPG analysis to achieve and improve fault coverage.

• Lead DFT insertion flows for SoC/ASIC designs.
• Perform scan chain insertion and integration using synthesis or equivalent tools.
• Implement compression scan technologies and LBIST strategies.
• Design and validate memory built-in self-test (MBIST) solutions.
• Generate ATPG patterns to meet design test coverage goals and follow systematic quality metrics.
• Debug and analyze test failures; improve fault coverage through iterative fixes.
• Verify ATPG testbenches and investigate simulation mis-compares to root cause issues.
• Collaborate with cross-functional teams (architecture, design, verification, customers) to deliver testable designs.
• Work independently to complete assigned DFT tasks on schedule.

Requirements

Key qualifications, with a concise separation of must-have and nice-to-have items.

• Must-have: 10–20 years of professional SoC/ASIC digital design experience with a primary focus on DFT.
• Must-have: Intimate knowledge of DFT insertion flows and practical scan chain insertion experience.
• Must-have: Experience with compression scan insertion, LBIST and other scan technologies.
• Must-have: Expertise in ATPG and demonstrated ability to meet test coverage targets.
• Must-have: Experience debugging failures, analyzing results, and verifying ATPG testbenches.
• Must-have: Working knowledge of JTAG (1149.1/6), IEEE 1500 and IEEE 1687.
• Must-have: Strong problem-solving skills and ability to work independently and in teams.
• Preference noted in posting: US citizenship preferred.
• Nice-to-have: Prior experience with Cadence tools and flows, hands-on Verilog testbench experience, and familiarity with timing analysis and equivalency checks.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.