Senior Principal Design Engineer — Memory Modeling Portfolio

Job Title

Senior Principal Design Engineer — Memory Modeling Portfolio

Role Summary

Senior design engineering architect on the Memory Model Portfolio (MMP) R&D team. Serve as the primary customer-facing expert for the UFS/Unipro/MPHY/RMMI protocol stack, working on-site to debug, integrate, and deploy memory protocol IP on hardware emulation platforms and to mentor R&D engineers.

Experience Level

Senior — typically requires 8+ years of relevant industry experience for PhD holders or 10+ years for Master's holders; equivalent experience may be considered.

Responsibilities

Primary responsibilities focus on customer engagement, technical problem solving, and driving product-quality improvements.

• Act as the primary customer interface for protocol integration, system-level debugging, and solutions consulting across the UFS/Unipro/MPHY/RMMI stack; be present on customer sites when needed.
• Help customers debug and characterize failures, translate symptoms into clear problem definitions for R&D, and scope fixes.
• Triage, analyze, and track field issues through to resolution; coordinate defect repair with R&D and maintain accountability to customers.
• Map customer requirements to product capabilities or gaps and present proposed solutions to technical and managerial audiences.
• Mentor and guide less experienced design engineers in protocol understanding, RTL code, and verification methodology.
• Participate actively in development lifecycle activities: design reviews, cross-verification, cross-training, and quality processes.
• Review RTL implementation approaches and provide technically grounded feedback to raise quality without blocking progress.
• Partner with internal account and field teams globally to ensure successful deployment and build long-term technical relationships.

Requirements

Must-have skills and attributes:

• Deep, demonstrable expertise in the full UFS/Unipro/MPHY/RMMI protocol stack.
• Fluent in SystemVerilog/Verilog RTL design and verification; able to write, review, and rigorously debug RTL in hardware emulation environments.
• Proven methodical debugging skills and discipline under customer pressure.
• Advanced English written and verbal fluency for global collaboration.
• Strong customer-facing, communication, and emotional-intelligence skills; able to translate customer problems into engineering tasks.
• Accountability for tracking issues to resolution and coordinating across teams.

Preferred / Nice-to-have:

• Hands-on experience with Cadence Palladium and/or Protium emulation platforms.
• Familiarity with scripting environments (Perl, TCL, C-shell).
• Breadth of protocol exposure beyond UFS (SDRAM families, NAND Flash, hybrid memory technologies).
• Experience navigating diverse customer behaviors and building long-term technical relationships across cultures.

Education Requirements

Master's degree in Electrical Engineering (or equivalent) with 10+ years of relevant industry experience, or PhD with 8+ years of relevant industry experience; equivalent practical experience accepted.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.