Senior Principal Design Engineer
Develop and enhance UVM-based functional verification environments for complex memory and interconnect IP. Ensure verification regressions, functional and code coverage targets, and team quality metrics are met. Provide support to customers and collaborate with design teams to resolve verification issues.
Senior — typically 10–12+ years of relevant experience, including design verification.
Primary responsibilities include:
Must-have and preferred qualifications:
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (BS/MS in EE/CE) as stated in the posting.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
