Senior Principal Design Engineer

Job Title

Senior Principal Design Engineer

Role Summary

Lead analog/mixed-signal design for die-to-die (D2D) and SERDES products on advanced CMOS nodes as part of a product development team. The role spans circuit design, verification, and close collaboration with layout and system architects to meet customer specifications.

Experience Level

Senior — requires substantial prior experience. The posting specifies a minimum of 8 years of CMOS IC design experience.

Responsibilities

Core responsibilities include end-to-end analog/mixed-signal design and collaboration across design, layout, verification, and global teams.

• Design high-speed D2D and SERDES products at industry-standard data rates on leading-edge nodes (example: 3nm FinFET CMOS).
• Develop analog/mixed-signal IC blocks from concept/specification through final verification against customer requirements.
• Collaborate closely with layout design engineers on IC blocks and PMA sections to ensure manufacturability and performance.
• Work with technical team leads on circuit design choices and SERDES architectures.
• Coordinate with global teams across time zones for design reviews, integration, and delivery.

Requirements

Must-have technical skills and experience followed by preferred qualifications.

• Must-have: Minimum of 8 years of CMOS IC design experience, preferably in CMOS SERDES or high-speed I/O IC design.
• Must-have: Strong understanding of jitter and signal equalization techniques.
• Must-have: Design experience with SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, low-jitter PLLs, high-speed clock distribution, bias and bandgap, and voltage regulators.
• Must-have: Proficiency with CAD tools for circuit simulation, layout and physical verification.
• Must-have: Excellent problem-solving ability, analog aptitude, clear communication, and ability to work in a team environment.
• Preferred / Nice-to-have: Experience with Cadence toolflows, design at >10 Gbps, technologies <16 nm, and lab test experience for silicon evaluation.

Education Requirements

BEng, MEng, PhD or equivalent practical experience. The posting states degree options (BEng, MEng, PhD) with allowance for equivalent experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.