Senior Principal ASIC FPGA Engineer

Job Title

Senior Principal ASIC FPGA Engineer

Role Summary

Hands-on technical lead responsible for defining architecture, leading RTL development, and driving complex ASIC/FPGA designs from concept through tape-out. Works with cross-functional teams on verification, synthesis, place-and-route, timing closure, and foundry/EDA tool selection.

Role requires independent problem solving, technical mentorship, and participation in program planning and reporting activities.

Experience Level

Senior — typically 8+ years experience; posting specifies 10+ years with a Bachelor's or 8+ years with a Master's.

Responsibilities

Primary technical and leadership responsibilities for ASIC/FPGA projects.

• Define technical approach, system partitioning, and microarchitecture from concept to silicon.
• Lead and review RTL development with focus on correctness, bus integrity, and clock domain crossings.
• Drive synthesis, place-and-route, and static timing analysis to achieve timing on advanced process nodes.
• Lead verification planning; own test and simulation plans and act as primary verification contact.
• Triage and prioritize team JIRA backlog; ensure backlog accuracy and progress tracking.
• Conduct RTL code reviews and provide constructive feedback to engineers.
• Contribute to program schedule planning (IMS) and Earned Value reporting.
• Evaluate foundry technologies and EDA tooling to inform design choices.
• Lead technical proposals and manage technical subcontract efforts as needed.
• Mentor junior and mid-level engineers and improve ASIC/FPGA design processes.

Requirements

Key must-have skills, experience, and employment constraints. Degrees and fields are listed separately under Education Requirements.

• Must-have: Department of Defense Secret security clearance required at time of hire.
• Must-have: U.S. citizenship required.
• Must-have: Expert-level RTL design skills and deep understanding of ASIC/FPGA engineering concepts.
• Must-have: Proven experience with synthesis, P&R, static timing analysis, and successful tape-out of complex silicon, preferably at advanced process nodes.
• Must-have: Strong experience with industry-standard EDA tools for synthesis, simulation, and verification.
• Must-have: Demonstrated ability to operate independently, lead technical decisions, and drive issue resolution.
• Nice-to-have: Experience evaluating foundry options and selecting EDA tool flows; prior responsibility for technical subcontracts and proposal development.
• Nice-to-have: Prior experience with program-level scheduling and Earned Value management.

Education Requirements

Bachelor's degree in Electrical or Computer Engineering or a related field with 10+ years of relevant experience, or a Master's degree with 8+ years of relevant experience. (The posting requires these degree/experience combinations.)

About the Company

Company: General Dynamics Mission Systems

Headquarters: Fairfax, Virginia, United States

Develops high-technology solutions, products and services for defense and scientific customers worldwide, including secure communications, mission systems, sensors, and ISR/C4ISR capabilities. Employs engineering, integration and program teams to support military and government missions.