Senior Principal ASIC Design Engineer

Job Title

Senior Principal ASIC Design Engineer

Role Summary

Lead technical design and delivery of high-performance networking ASIC subsystems from architecture through final netlist. Work within the HPE Networking Silicon organization to define subsystem architecture, implement RTL, and collaborate across product, verification, software, and physical design teams.

One short motivating sentence: contribute technical leadership that directly impacts high-performance routing and switching silicon at scale.

Experience Level

Senior-level. The posting requests candidates with 15+ years of relevant ASIC design experience.

Responsibilities

Primary responsibilities include subsystem architecture, RTL implementation, and cross-functional technical leadership.

• Define architecture and create detailed specifications for complex ASIC subsystems.
• Translate product, hardware, and software requirements into implementable micro-architecture and RTL.
• Implement complex RTL modules using Verilog/SystemVerilog with emphasis on quality, reuse, and timing closure.
• Develop functional coverage and SystemVerilog Assertions to improve verification quality.
• Apply power-reduction techniques during architecture and implementation to meet aggressive power targets.
• Collaborate with physical design on floorplanning, timing closure, and RTL timing fixes to achieve frequency goals.
• Work with verification teams to validate blocks for functional, performance, and integration requirements.
• Provide technical leadership and mentor engineers across the design team.
• Drive methodology improvements, automation, and pragmatic use of AI-assisted tools to accelerate design and review workflows.
• Lead architecture-level trade-offs across subsystems balancing performance, power, area, timing, verification, software, and manufacturability.

Requirements

Must-have technical skills and experience; preferred items listed where applicable.

• 15+ years of ASIC design experience, with demonstrated leadership as a chip or subsystem lead.
• Proven experience architecting and implementing high-performance ASIC subsystems from specification through final netlist.
• Strong RTL coding skills in Verilog and SystemVerilog.
• Experience with synthesis flows and advanced EDA tools (lint, CDC, formal) used in modern ASIC development.
• Experience in at least two of: 10G–800G Ethernet interface standards; HBM2/HBM2E/DDR4 or similar memory integration; security protocols (MACsec/IPsec); networking protocols and deep packet inspection; schedulers, queuing and memory subsystems; fixed-function or microcode-based packet processing.
• Practical knowledge of power optimization and timing/power/area trade-offs in high-frequency designs.
• Working knowledge of scripting for automation (Perl, Python) and familiarity with automation frameworks.
• Excellent written and verbal communication and demonstrated ability to work cross-functionally.
• Nice-to-have: prior first-authored patents in networking or computer architecture; multiple successful tape-outs and full-chip leadership experience.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; a Master’s degree is preferred. The posting does not state an explicit equivalent-experience substitution for the degree requirement.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.