Senior Principal Applied ML Engineer

Job Title

Senior Principal Applied ML Engineer

Role Summary

Lead design and delivery of production-grade AI agent infrastructure and evaluation systems for Cadence’s ChipStack SuperAgent platform. Work with ML scientists and software engineers to integrate reliable, scalable agentic systems into semiconductor design and verification workflows.

Focus areas include agent infrastructure, retrieval and data pipelines, evaluation frameworks, CI/testing, and operational observability for large-scale ML deployments.

Experience Level

Senior-level. Typical experience guidance: BS + 10 years, MS + 7 years, or PhD + 5 years (see Education Requirements for full details).

Responsibilities

Deliver engineering and ML system work that enables agent-driven EDA workflows.

• Design and implement scalable infrastructure for AI agents within the ChipStack SuperAgent ecosystem.
• Build robust evaluation and benchmarking frameworks to measure agent performance, reliability, and alignment with engineering workflows.
• Develop data pipelines, retrieval systems, and context-engineering strategies to support grounded agent behavior (RAG, embeddings, indexing).
• Integrate CI, automated testing, logging, tracing, and observability for production ML systems.
• Optimize system performance across latency, cost, reliability, and scalability trade-offs.

Requirements

Must-have technical skills and experience; candidate should demonstrate production delivery and practical ML systems knowledge.

• Must-have: Strong software engineering fundamentals for complex distributed systems (design, refactoring, debugging, testing) and demonstrated production-quality delivery.
• Must-have: Practical experience with deploying large language models (LLMs) in production addressing latency, cost, reliability, and monitoring.
• Must-have: Experience designing evaluation frameworks for AI systems, including benchmarking, regression testing, and failure analysis.
• Must-have: Experience building data/retrieval pipelines (RAG patterns, embeddings, chunking, indexing) to ground model behavior.
• Must-have: Experience implementing CI/CD, automated testing, logging/tracing, and observability for ML/AI applications.
• Nice-to-have: Agent architecture experience (reason–act loops, planning, tool/function calling, persistent memory, structured outputs).
• Nice-to-have: LLM engineering skills (prompt engineering, context management, alignment techniques) and familiarity with frontier model families.
• Nice-to-have: Interest or experience in semiconductor design, EDA workflows, and high-performance computing environments.

Education Requirements

Required: Bachelor's degree with a minimum of 10 years' relevant experience, OR Master's degree with a minimum of 7 years' relevant experience, OR PhD with a minimum of 5 years' relevant experience. No specific field of study mandated in the posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.