Senior Principal Application Engineer — RTL-to-GDS (Digital Implementation & Signoff)

Job Title

Senior Principal Application Engineer — RTL-to-GDS (Digital Implementation & Signoff)

Role Summary

Expert Field Applications Engineer focused on digital implementation and signoff. You will work directly with semiconductor customers to deploy and optimize Synthesis, Place & Route, and timing/power signoff flows to meet PPA and schedule targets.

You will also collaborate with Cadence R&D to capture customer requirements, influence product direction, and improve tools and methodologies.

Experience Level

Senior — requires 10+ years of industry physical design experience (physical/backend digital implementation and signoff).

Responsibilities

Primary responsibilities include technical customer engagement, solution delivery, and feedback to R&D.

• Provide technical support to customers in backend digital design implementation and signoff (place & route, timing and power closure, IR drop).
• Advise customers on tool selection and flow optimizations to meet PPA and project schedules.
• Plan and execute technical evaluations, benchmarks, and proofs-of-concept.
• Deliver technical presentations and product demonstrations to customers and internal teams.
• Work with R&D to translate customer requirements into product enhancements and roadmap input.
• Develop and modify flows using scripting (Tcl, Python, etc.) to automate tasks and improve results.
• Capture best practices and lessons learned and disseminate them to teams and customers.
• Drive adoption and proliferation of Cadence technologies within customer environments.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 10+ years of industry physical design experience focused on backend digital implementation and signoff.
• Must-have: Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
• Must-have: Hands-on experience with IC digital implementation flows and backend EDA tools (place & route, IR drop, timing and power closure).
• Must-have: Experience with advanced process nodes (10 nm and below).
• Must-have: Proficiency in scripting languages such as Tcl, Perl, or Python.
• Must-have: Strong customer-facing communication, problem-solving skills, and self-driven continuous learning.
• Nice-to-have: Experience with front-end EDA tools (synthesis, DFT, logical equivalence checking) and with Cadence toolset (Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC/ICC2, DC, PrimeTime).
• Nice-to-have: Hands-on experience at advanced nodes 5 nm and below.

Education Requirements

Required: Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field. Preferred: Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.